METHOD FOR TRANSFERRING SELF-ASSEMBLED DUMMY PATTERN TO SUBSTRATE

• US 20080124906A1
• Filed: 12/30/2006
• Published: 05/29/2008
• Est. Priority Date: 11/24/2006
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Moon, Jae In
• Granted Patent: US 7,712,070 B2
• Time in Patent Office: Days
• US Class Current: 438/584
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

A semiconductor device fabrication method is disclosed. The method includes obtaining an inverse layout of an original circuit layout, reducing the inverse layout in size, thereby obtaining a reduced layout, obtaining a dummy pattern layout having an outline identical to an outline of the reduced layout and a given line width such that the dummy pattern layout is self-assembled to the circuit layout, and transferring the self-aligned or self-assembled dummy pattern layout and circuit layout to a semiconductor substrate.

Claims

1. A method for transferring patterns to a substrate, comprising:

designing a circuit layout to be transferred to the substrate;

obtaining an inverse layout of the circuit layout;

reducing the inverse layout in size, thereby obtaining a reduced layout;

obtaining a dummy pattern layout having an outline corresponding to an outline of the reduced layout and a given line width such that the dummy pattern layout is self-assembled to the circuit layout; and

combining the dummy pattern layout and the circuit layout.

2. The method of claim 1, further comprising:

transferring the circuit layout to the substrate.

3. The method of claim 1, further comprising:

transferring the combined layout to the substrate

4. The method according to claim 1, wherein the circuit layout is designed as a layout of metal lines of a memory device, wherein the substrate is a semiconductor substrate.

5. The method according to claim 1, wherein the circuit layout is designed as a layout of bit lines constituting a page buffer circuit of a flash memory device.

6. The method according to claim 1, wherein the circuit layout is designed as an arrangement layout of connecting contacts for a line connecting structure.

7. The method according to claim 1, further comprising:

reducing the inverse layout by a reduction width larger than a reduction width of the reduced layout, thereby obtaining a second reduced layout;

obtaining a second dummy pattern layout having an outline corresponding to an outline of the second reduced layout and a given line width such that the second dummy pattern layout is spaced apart from the circuitry layout farther than the first dummy pattern; and

combining the second dummy pattern layout and the circuitry layout.

8. The method according to claim 1, further comprising:

transferring the combined layout to a photomask substrate, thereby forming a photomask; and

performing a light exposure process using the photomask, thereby transferring the combined layout to the substrate.

9. The method according to claim 8, wherein the light exposure process is performed under light exposure conditions including a symmetrical illumination or an asymmetric illumination.

10. The method according to claim 8, wherein the photomask comprises a binary mask or a phase shift mask.

11. A method for transferring a pattern to a substrate, comprising:

designing a circuit layout having a circuit pattern, the circuit pattern defining an open area;

obtaining an inverse layout of the circuit layout;

reducing the inverse layout by a first reduction width, thereby obtaining a first reduced layout;

reducing the first reduced layout by a second reduction width, thereby obtaining a second reduced layout;

deducting the second reduced layout from the first reduced layout, thereby obtaining a self-assembled dummy pattern layout ;

combining the dummy pattern layout and the circuit layout, the dummy pattern layout being defined within an open area defined by the circuit pattern; and

transferring the combined layout to a substrate.

12. The method of claim 11, wherein the substrate to where the combined layout is transferred is a semiconductor substrate.

13. The method of claim 11, wherein the substrate to where the combined layout is transferred is a photomask substrate.

14. The method according to claim 11, wherein the circuit layout is designed as a layout of bit lines constituting a page buffer circuit of a flash memory device.

15. The method according to claim 11, further comprising:

reducing the second reduced layout by a third reduction width, thereby obtaining a third reduced layout;

reducing the third reduced layout by a fourth reduction width, thereby obtaining a fourth reduced layout;

deducting the fourth reduced layout from the third reduced layout, thereby obtaining a second dummy pattern layout; and

combining the second dummy pattern layout and the circuit layout.

16. The method according to claim 11, further comprising:

reducing the inverse layout by a reduction width larger than the second reduced width, thereby obtaining a second reduced layout;

obtaining a second dummy pattern layout having an outline corresponding to an outline of the third reduced layout and a given line width such that the second dummy pattern layout is spaced apart from the circuit layout, farther than the first dummy pattern;

combining the second dummy pattern layout and the circuit layout.

17. A method for fabricating a semiconductor device, comprising:

designing a circuit layout;

setting light exposure conditions to be used for transfer of the circuit layout;

obtaining an inverse layout of the circuit layout;

reducing the inverse layout in an X-axis direction by a first reduction width set after reflecting the light exposure conditions in association with the X-axis direction, thereby obtaining a first reduced layout;

reducing the first reduced layout in a Y-axis direction by a second reduction width set after reflecting the light exposure conditions in association with the Y-axis direction, thereby obtaining a second reduced layout;

reducing the second reduced layout by a third reduction width in the X-axis direction and by a fourth reduction width in the Y-axis direction, thereby obtaining a third reduced layout;

deducting the third reduced layout from the second reduced layout, thereby obtaining a dummy pattern layout self-assembled to the circuit layout;

combining the dummy pattern layout and the circuit layout; and

transferring the combined layout to a semiconductor substrate.

18. The method according to claim 17, wherein the original circuit layout is designed as a circuit layout of metal lines of a memory device.

19. The method according to claim 17, wherein the circuit layout is designed as a layout of bit lines constituting a page buffer circuit of a flash memory device.

20. The method according to claim 17, wherein the circuit layout is designed as an arrangement layout of connecting contacts for a line connecting structure.

21. The method according to claim 17, wherein the light exposure conditions include a symmetrical illumination having the same exposure resolution in X-axis and Y-axis directions or an asymmetrical illumination having different exposure resolutions in X-axis and Y-axis directions.

22. The method according to claim 17, wherein the first and second reduction widths are set to be equal to each other or to be different from each other, depending on the light exposure conditions.

23. The method according to claim 17, further comprising:

reducing the third reduced layout by a fifth reduction width in the X-axis direction and by a sixth reduction width in the Y-axis direction, thereby obtaining a fourth reduced layout;

reducing the fourth reduced layout by a seventh reduction width in the X-axis direction and by an eighth reduction width in the Y-axis direction, thereby obtaining a fifth reduced layout;

deducting the fifth reduced layout from the fourth reduced layout, thereby obtaining a second dummy pattern layout; and

combining the second dummy pattern layout and the circuit layout.

24. The method according to claim 17, further comprising:

obtaining a fourth reduced layout reduced from the inverse layout such that the fourth reduced layout is spaced apart from the circuit layout, farther than the first dummy pattern;

obtaining a second dummy pattern layout having an outline identical to an outline of the fourth reduced layout and a given line width; and

combining the second dummy pattern layout and the circuit layout.