Circuit for classifying signals

• US 20080125989A1
• Filed: 08/14/2006
• Published: 05/29/2008
• Est. Priority Date: 08/14/2006
• Status: Active Grant

• Current Assignee: University of Washington
• Original Assignee: University of Washington
• Inventors: Diorio, Chris, Mavoori, Jaideep
• Granted Patent: US 7,525,349 B2
• Time in Patent Office: Days
• US Class Current: 702/66
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602

Abstract

A circuit for classification of analog input signals, comprising an analog memory component, such as a floating gate, used to store a threshold value; a threshold detection module used to determine whether the analog input signal exceeds the threshold value; a time delay module used to delay a processing of the analog signal; a time-amplitude window calculation module used to determine whether an amplitude of the analog input signal is between a lower limit and an upper limit of an amplitude window; and an output module indicating whether the amplitude of the analog signal is between the lower and the upper limit, wherein the indication is used to determine whether the analog input signal belongs to one of a plurality of analog signal classes. The classification is implemented in the analog domain, eliminating the need for sampling and digitizing the analog signal, consequently minimizing circuit area and power.

Claims

1. A circuit for classification of analog input signals, the circuit comprising:

a first analog memory component operative to store a threshold value;

a threshold detection module operative to determine whether the analog input signal exceeds the threshold value;

a time delay module operative to delay a processing of the analog input signal by an amount equal to a window time delay;

an amplitude window calculation module operative to determine, after a lapse of the window time delay, whether an amplitude of the analog input signal is between a lower limit and an upper limit of an amplitude window; and

an output module providing an indication of whether the amplitude of the analog input signal is between the lower limit and the upper limit of the amplitude window, wherein the indication is used to determine whether the analog input signal belongs to at least one of a plurality of pre-determined classes of analog signals.

2. The circuit of claim 1, wherein the first analog memory component comprises a floating gate of a transistor.

3. The circuit of claim 1, wherein the analog signal amplitude window determination module comprises an electronic operational amplifier having an inverting and a non-inverting input terminal.

4. The circuit of claim 1, wherein the time delay module delays the processing of the analog input signal by disabling the analog signal amplitude window determination module for a period of time equal to the predetermined time delay.

5. The circuit of claim 1, wherein the threshold value comprises an electrical charge corresponding to a first numerical value of the analog input signal.

6. The circuit of claim 1, wherein the lower limit and the upper limit of the amplitude window comprise electrical charges stored in a second and a third analog memory component, respectively.

7. The circuit of claim 1, wherein the indication provided by the output module comprises at least one digital signal indicating whether the amplitude of the analog input signal is greater than the lower limit and less than the upper limit.

8. The circuit of claim 7, wherein the output module comprises a logic circuit for logically combining results of the determination of the amplitude of the analog input signal being greater than the lower limit and less than the upper limit and outputting the at least one digital signal.

9. The circuit of claim 1, wherein the time delay module comprises an analog delay circuit.

10. The circuit of claim 9, wherein the analog delay circuit comprises a first delay analog memory component, a second delay analog memory component, a capacitor, and a delay operational amplifier.

11. The circuit of claim 10, wherein the first delay analog memory component is used to store an electrical charge corresponding to a rate of electrical charge-up of the capacitor.

12. The circuit of claim 11, wherein the capacitor provides an electrical charge-up delay corresponding to the window time delay.

13. The circuit of claim 10, wherein the second delay analog memory component is used to set the maximum electrical charge held by the capacitor.

14. The circuit of claim 1, wherein the time delay module comprises a digital delay circuit.

15. The circuit of claim 14, wherein the digital delay circuit comprises a counter component, a compare register component operable to store a digital value corresponding to a time delay value, and a digital comparator component operable to compare an output of the counter component and the digital value corresponding to the time delay value.

16. An array of analog circuits for detection of patterns of analog input signals, the array of analog circuits comprising:

a plurality of input ports operative to receive a plurality of analog input signals;

a plurality of circuits, corresponding to the plurality of the input ports, each operative to receive one of the plurality of the analog input signals, each circuit comprising;

a first analog memory component operative to store a threshold value;

a threshold detection module operative to determine whether the analog input signal exceeds the threshold value;

a time delay module operative to delay a processing of the one of the analog input signals by an amount equal to a corresponding window time delay;

an amplitude window calculation module operative to determine, after a lapse of the corresponding window time delay, whether an amplitude of the one of the analog input signals is between a corresponding lower limit and a corresponding upper limit of a corresponding amplitude window; and

an output module providing an indication of whether the amplitude of the one of the analog input signals is between the corresponding lower and the corresponding upper limit of the corresponding amplitude window, wherein the indication is used to determine whether the one of the analog input signals belongs to at least one of a plurality of predetermined classes of analog signals; and

an array control module operative to select one of the plurality of the circuits.

17. The array of analog circuits of claim 16, wherein the plurality of the analog input signals are pre-amplified before being received by the plurality of the input ports.

18. The array of circuits of claim 16, wherein the plurality of the circuits are connected to at least an address bus for selecting one of the plurality of the circuits, an analog bus for delivering the plurality of the analog input signals to a signal processor, and a spike bus for delivering the indications provided by each of the output modules of the plurality of the circuits to the signal processor.

19. The array of circuits of claim 18, wherein the array control module comprises an address decoder for selecting one of the plurality of the circuits using at least one of the address bus, the analog bus, and the spike bus.

20. A device for detection of patterns of analog input signals, the device comprising:

an array of circuits;

a plurality of input ports operative to receive a plurality of analog input signals;

a plurality of circuits, corresponding to the plurality of the input ports, each operative to receive one of the plurality of the analog input signals, each circuit comprising;

a first analog memory component operative to store a threshold value;

a threshold detection module operative to determine whether the analog input signal exceeds the threshold value;

a time delay module operative to delay a processing of the one of the analog input signals by an amount equal to a corresponding window time delay;

an amplitude window calculation module operative to determine, after a lapse of the corresponding window time delay, whether an amplitude of the one of the analog input signals is between a corresponding lower limit and a corresponding upper limit of a corresponding amplitude window; and

an output module providing an indication of whether the amplitude of the one of the analog input signals is between the corresponding lower and the corresponding upper limit of the corresponding amplitude window, wherein the indication is used to determine whether the one of the analog input signals belongs to at least one of a plurality of pre-determined classes of analog signals;

an array control module operative to select one of the plurality of the circuits; and

a communication interface module operative to transfer information to/from the analog device.

21. The analog device of claim 20 further comprising a power source to power the analog circuits.

22. The analog device of claim 20, wherein an external power source is used to power the analog circuits.

23. The analog device of claim 20, wherein the communication interface module comprises a serial interface.

24. The analog device of claim 20, wherein the communication interface module comprises a wireless communication interface.

25. A method for classification of analog signals, the method comprising:

receiving an analog input signal;

in response to receiving the analog input signal, detecting an amplitude of the analog input signal crossing a threshold stored in a first analog memory component;

in response to detecting the amplitude of the input signal crossing the threshold, waiting an amount of time and comparing the amplitude of the input signal to a lower and an upper limit of an amplitude window;

indicating whether the amplitude of the analog input signal is between the lower and the upper limits of the amplitude window; and

using the indication to determine whether the analog input signal belongs to at least one of a plurality of pre-determined classes of analog signals.

26. The method of claim 25, wherein the input signal is provided by an analog signal source.

27. The method of claim 26, wherein the analog signal source comprises live neural tissue.

28. The method of claim 26, wherein the analog signal source comprises a photo sensor.

29. The method of claim 26, wherein the analog signal source comprises a pressure sensor.

30. The method of claim 26, wherein the analog signal source comprises a thermal sensor.

31. The method of claim 26, wherein the analog signal source comprises a seismic motion sensor.

32. The method of claim 25, wherein waiting an amount of time comprises using a time delay module to delay a processing of the input signal.

33. The method of claim 25, wherein the comparing of the amplitude of the input signal to a lower and an upper limit of an amplitude window comprises using an analog comparator component for the comparison.

34. The method of claim 25, wherein the lower and the upper limits of the amplitude window are stored in a second and a third analog memory component, respectively.

35. A method for detection of patterns of signals, the method comprising:

receiving a plurality of analog input signals;

in response to receiving each one of the plurality of analog input signals, detecting an amplitude of each one of the analog input signals crossing a corresponding threshold;

for each of a plurality of positive amplitude peaks and each of a plurality of negative amplitude peaks of each of the plurality of the analog input signals, respectively;

waiting a corresponding amount of time, stored in a corresponding first analog memory component, and comparing the positive amplitude peak and the negative amplitude peak of each of the plurality of analog input signals, respectively, to one of a plurality of lower limits and one of a plurality of upper limits, respectively, of a plurality of corresponding amplitude windows;

indicating whether each of the positive amplitude peaks and each of the negative amplitude peaks of each of the analog input signals is between the corresponding one of the plurality of the lower limits and the corresponding one of the plurality of the upper limits; and

determining, based on the indication for each of the analog input signals, whether each of the analog input signals matches one of a plurality of predetermined signal patterns.

36. The method of claim 35, wherein each of the plurality of the input signals is provided by an analog signal source.

37. The method of claim 35, wherein each of the plurality of the positive amplitude peaks and each of the plurality of the negative amplitude peaks is stored in a corresponding second and third analog memory component, respectively.

38. The method of claim 35, wherein the plurality of the input signals are received by a corresponding plurality of analog signal classifiers organized in a row-addressable and column-addressable array of signal classifiers.

39. The method of claim 38, wherein an output of the array of signal classifiers is multiplexed to provide an output signal of a signal classifier corresponding to a selected row and a selected column of the array of signal classifiers.

40. The method of claim 39, wherein the output of the array of signal classifiers is provided to a signal processor for performing further computations on the plurality of the input signals.

41. A method for classification of signals, the method comprising:

storing an analog threshold value in a first analog memory component;

storing an analog value, based on which a corresponding time-delay value is determined, in a second analog memory component;

storing an analog lower limit of an amplitude window in a third analog memory component;

storing an analog upper limit of an amplitude window in a fourth analog memory component;

receiving an analog input signal;

in response to receiving the analog input signal, detecting an amplitude of the analog input signal crossing the analog threshold value;

in response to detecting the amplitude of the analog input signal crossing the analog threshold value, waiting an amount of time equal to the analog time-delay value and comparing the amplitude of the analog input signal to the analog lower limit and the analog upper limit of the amplitude window;

indicating whether the amplitude of the analog input signal is between the analog lower limit and the analog upper limit of the amplitude window; and

using the indication to determine whether the analog input signal belongs to at least one of a plurality of predetermined classes of analog signals.

42. The method of claim 41, wherein the first, second, third, and fourth analog memory components comprise a floating gate of a transistor.

43. The method of claim 41, wherein the analog input signal is provided by an analog signal source.

44. The method of claim 41, wherein the storing of the analog threshold value, the analog time-delay value, the analog lower limit, and the analog upper limit is performed via a controller module coupled with the first, second, third, and fourth analog memory components, respectively.