Network on chip (NoC) response signal control apparatus and NoC response signal control method using the apparatus

• US 20080126569A1
• Filed: 01/11/2007
• Published: 05/29/2008
• Est. Priority Date: 09/13/2006
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Beom Hak, Kim, Eui Seok, Rhim, Sang Woo
• Application Number:
  US11/652,010
• Publication Number:
  US 20080126569A1
• Time in Patent Office: Days
• US Class Current: 709/250
• CPC Class Codes: G06F 15/7825 Globally asynchronous, locally synchronous, e.g. network on chip

Abstract

A network on chip (NoC) response signal control apparatus and an NoC response signal control method using the apparatus are provided. The NoC response signal control apparatus includes: a network interface (NI) slave which outputs an enabling signal for a response signal via a response signal wire if a predetermined response signal is input from a slave intellectual property (IP); and an NI master which outputs a transaction to a master IP by generating the transaction for the response signal if the enabling signal is input via the response signal wire which is directly connected to the NI slave.

Claims

1. A network on chip (NoC) response signal control apparatus comprising:

a network interface (NI) slave which outputs an enabling signal for a response signal via a response signal wire if a predetermined response signal is input from a slave intellectual property (IP); and

an NI master which outputs a transaction to a master IP by generating a transaction for the response signal if the enabling signal is input via the response signal wire which is directly connected to the NI slave.

2. The apparatus of claim 1, wherein the response signal wire is a one-bit wire.

3. The apparatus of claim 2, wherein the transaction is an advanced extensible interface transaction.

4. The apparatus of claim 3, wherein the NI master generates the transaction for the response signal using an aWID signal which is input from the master IP, when the enabling signal is input.

5. The apparatus of claim 3, wherein the NI master outputs an enabling signal for the response signal via the response signal wire if an ‘

Okay’

response signal is input from the slave IP.

6. The apparatus of claim 2, wherein the response signal wire directly connects a decoder in the NI master to a packet builder in the NI slave.

7. The apparatus of claim 1, wherein the response signal wire is a five-bit wire if the NI master supports multiple outstanding mode.

8. The apparatus of claim 7, wherein the enabling signal includes a four-bit bID signal if the transaction is an advanced extensible interface transaction.

9. The apparatus of claim 1, wherein the transaction is one of an advanced microcontroller bus architecture high-performance bus transaction, and an open core protocol transaction.

10. A network on chip (NoC)response signal control method comprising:

outputting an enabling signal for a response signal via a response signal wire if a predetermined response signal is input from a slave intellectual property (IP);

outputting a transaction to a master IP by generating the transaction for the response signal if the enabling signal is input to a network interface (NI) master via the response signal wire which is directly connected to an NI slave.

11. The method of claim 10, wherein the response signal wire is a one-bit wire.

12. The method of claim 11, wherein a type of the transaction is an advanced extensible interface transaction.

13. The method of claim 12, wherein the outputting the transaction comprises:

generating the transaction for the response signal using an aWID signal which is input from the master IP, and

outputting the transaction for the generated response signal to the master IP.

14. The method of claim 12, wherein the outputting the enabling signal comprises outputting the enabling signal for the response signal via the response signal wire if an ‘

Okay’

response signal is input from the slave IP.

15. The method of claim 11, wherein the outputting of the enabling signal comprises outputting the enabling signal, which is generated by a packet builder in the NI slave, to a decoder in the NI master via the response signal wire if the response signal is input from the slave IP to the NI slave.

16. The method of claim 10, wherein the response signal wire is a five-bit wire if the NI master supports multiple outstanding mode.

17. The method of claim 16, wherein the enabling signal includes a four-bit bID signal if the transaction is an advanced extensible interface transaction.

18. The method of claim 10, wherein the transaction is one of an advanced microcontroller bus architecture high-performance bus transaction, and an open core protocol transaction.

19. A computer-readable storage medium storing a program for implementing the a network on chip (NoC)response signal control method comprising:

outputting an enabling signal for a response signal via a response signal wire if a predetermined response signal is input from a slave intellectual property (IP);

outputting a transaction to a master IP by generating the transaction for the response signal when the enabling signal is input to a network interface (NI) master via the response signal wire which is directly connected to an NI slave.