INTERFACE ARCHITECTURE FOR CONFIGURING A SERIAL CONTROLLER

• US 20080126587A1
• Filed: 01/18/2007
• Published: 05/29/2008
• Est. Priority Date: 06/21/2006
• Status: Active Grant

• Current Assignee: II-VI Delaware, Inc. (Coherent Corp.)
• Original Assignee: Finisar Corporation (II-VI Incorporated)
• Inventors: Dybsetter, Gerald L.
• Granted Patent: US 7,908,406 B2
• Time in Patent Office: Days
• US Class Current: 710/11
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Abstract

An architecture and method in an integrated circuit for configuring a controller to facilitate communication with a plurality of external device interfaces. The integrated circuit includes a processor, a first memory, a second memory, including a plurality of dedicated memory blocks containing configuration data, and a plurality of external device interfaces. The processor is configured to write a microcode instruction to the first memory. The controller is configured to read the microcode instruction in the first memory and as a result access one of the plurality of dedicated memory blocks. Next, the controller processes the configuration data in the dedicated memory block according to the microcode instruction. As a result, the controller is configured to communicate with one of the plurality of external device interfaces. This process may be repeated as needed to configure the controller to communicate with different device interfaces using different communication protocols.

Claims

1. In an integrated circuit including a processor, a first memory, a second memory including a plurality of dedicated memory blocks that contain interface configuration data, a controller, and a plurality of device interfaces for coupling the integrated circuit to a plurality of external devices, each device interface supporting a protocol, a method for configuring the controller to facilitate communication with each external device interface regardless of protocol, the method comprising:

an act of the processor writing command request control data to the first memory, the command request control data control data including a pointer to one of the plurality of dedicated memory blocks in the second memory and a controller command;

an act of the controller reading the command request control data in the first memory and accessing the interface configuration data stored in the one of the plurality of dedicated memory blocks corresponding to the pointer;

an act of the controller processing the accessed configuration data as directed by the controller command; and

as a result of processing, an act of the controller being configured to communicate with one of the plurality of external device interfaces using the protocol supported by the device interface.

2. A method in accordance with claim 1, wherein the second memory further includes one or more data areas that the controller may read data from or write data to.

3. A method in accordance with claim 1, wherein the configuration data includes an operation code directing the controller to read or write data received from the external device interface or provided to the external device interface, and wherein the configuration data includes the number of bytes of data to be transferred between the controller and the external device interface.

4. A method in accordance with claim 2, wherein the configuration data includes an address for the one or more data areas of the second memory.

5. A method in accordance with claim 1, wherein the configuration data includes a memory address and a device address for an external device coupled to the integrated circuit.

6. A method in accordance with claim 1, wherein the controller command is at least one of a command to save the configuration data, load the configuration data, or execute the configuration data.

7. A method in accordance with claim 1 further including:

an act of the controller writing a completion status command to the first memory; and

an act of the processor polling the first memory for the completion status command or receiving an interrupt.

8. A method in accordance with claim 1 further including:

an act of the controller communicating with an external device interface by sending data to and receiving data from the external device interface using the protocol supported by the external device interface.

9. A method in accordance with claim 1 further including:

an act of repeating the acts of the processor writing the command request control data to the first memory, the controller reading the command request control data in the first memory and accessing the interface configuration data stored in the one of the plurality of dedicated memory blocks corresponding to the pointer, and the controller processing the configuration data as directed by the controller command so as to configure the controller to communicate with a different one of the plurality of external device interfaces using a different protocol.

10. An integrated circuit comprising:

a first memory;

a microprocessor configured to write command request control data to the first memory, wherein command request control data includes a pointer and a controller command;

a second memory configured to include a plurality of dedicated memory blocks that contain interface configuration data; and

a controller configured to read the command request control data written in the first memory, access the interface configuration data stored in the one of the plurality of dedicated memory blocks corresponding to the pointer, and process the accessed configuration data as directed by the controller command, so as to configure the controller to communicate with one of a plurality of external device interfaces using a protocol supported by the external device interface.

11. An integrated circuit in accordance with claim 10 further including:

a memory access controller for facilitating controller access to the second memory and microprocessor access to the first memory.

12. An integrated circuit in accordance with claim 10, wherein the controller includes a master serial controller with direct memory access and a serializer/deserializer.

13. An integrated circuit in accordance with claim 12, wherein the serial controller and the serializer/deserializer are included in one component.

14. An integrated circuit in accordance with claim 12, wherein the serial controller and the serializer/deserializer are separate components.

15. An integrated circuit in accordance with claim 10, wherein the integrated circuit is implemented in a laser transmitter/receiver.

16. An integrated circuit in accordance with claim 15, wherein the laser transmitter/receiver is one of a 1 G laser transceiver, 2 G laser transceiver, 4 G laser transceiver, 8 G laser transceiver, or 10 G laser transceiver.

17. An integrated circuit in accordance with claim 15, wherein the laser transmitter/receiver is a laser transceiver suitable for fiber channels greater than 10 G.

18. An integrated circuit in accordance with claim 15, wherein the laser transmitter/receiver is one of an XFP laser transceiver, an SFP laser transceiver, or a SFF laser transceiver.

19. An integrated circuit in accordance with claim 10, wherein the controller is a state machine

20. A computing architecture for configuring a controller to communicate with a plurality of external device interfaces comprising:

a register;

a microprocessor configured to write command request control data to the register, wherein the command request control data includes a pointer and a controller command;

a system memory including a plurality of dedicated memory blocks that contain interface configuration data; and

a controller configured to read the command request control data written in the register, access the interface configuration data stored in the one of the plurality of dedicated memory blocks corresponding to the pointer, and process the configuration data as directed by the controller command, so as to configure the controller to communicate with one of a plurality of external device interfaces using a protocol supported by the external device interface.

21. A computing architecture in accordance with claim 20 wherein the configuration data includes at least one of an operation code directing the controller to read or write data from an external device, the number of bytes of data to be transferred between the controller and the external device interface, or a memory and device address of the external device.

22. A computing architecture in accordance with claim 20, wherein the controller command is at least one of a command to save the configuration data, load the configuration data, or execute the configuration data.