Embedded system and communication method thereof

• US 20080126610A1
• Filed: 12/08/2006
• Published: 05/29/2008
• Est. Priority Date: 09/05/2006
• Status: Abandoned Application

• Current Assignee: Shenzhen Mindray Bio-Medical Electronics Co., Ltd. (Excelsior Union Ltd.), Shenzhen Mindray Scientific Co., Ltd.
• Original Assignee: Shenzhen Mindray Bio-Medical Electronics Co., Ltd. (Excelsior Union Ltd.)
• Inventors: He, Bo, Wu, Xiaoyu, Cen, Jian
• Application Number:
  US11/636,223
• Publication Number:
  US 20080126610A1
• Time in Patent Office: Days
• US Class Current: 710/30
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines

Abstract

A system comprises an embedded processor A, a processor or equipment B and a FPGA/CPLD module, wherein a synchronous serial port of the embedded processor A is connected with the FPGA/CPLD module; in which a transmission clock and transmission frame synchronization signal are taken as output, while a receiving clock and receiving frame synchronization signal are taken as input; and a communication interface of the processor or equipment B is connected with the FPGA/CPLD module. This system ensures that the data transmitting party always take initiatives during communications with processor of equipment B. Via the FPGA/CPLD module, the system may interface with other systems through different communication protocols, such that the system need not modify its solutions to adapt to different protocols, but only upgrades the logic of the FPGA/CPLD to adapt to the new interfaces. As such, a high-speed, reliable and flexible communication mechanism is established.

Claims

1. An embedded system, comprising:

an embedded processor A;

a processor or equipment B; and

a FPGA/CPLD module;

wherein a synchronous serial port of the embedded processor A is connected with the FPGA/CPLD module;

in which a transmission clock and transmission frame synchronization signal are taken as output, while a receiving clock and receiving frame synchronization signal are taken as input; and

the communication interface of the processor or equipment B is connected with the FPGA/CPLD module.

2. The embedded system of claim 1, wherein it comprises one or more processors or equipments B.

3. The embedded system of claim 2, wherein each processor or equipment B has same or different communication protocol.

4. A communication method for an embedded system, comprising data transmitting from a processor A to a processor or equipment B, which transmitting particularly comprises the following steps:

the processor A transmits data to a FPGA/CPLD module according to a communication protocol A′

thereof;

the FPGA/CPLD module performs format conversion on the data from the processor A according to a communication protocol B′

of the processor or equipment B; and

the FPGA/CPLD module then forwards the converted data to the processor or equipment B.

5. The communication method of claim 4, further comprising data transmitting from the processor or equipment B to the processor A, which transmitting particularly comprises the following steps:

the processor or equipment B transmits data to the FPGA/CPLD module according to the communication protocol B′

thereof;

the FPGA/CPLD module performs format conversion on the data according to the communication protocol A′

of the processor A; and

the FPGA/CPLD module then forwards the converted data to the processor A.

6. The communication method of claim 4, further comprising the following step:

where there are two or more processors or equipments B, the processor A adds a channel flag bit to the transmitted data so as to indicate communication channel.

7. The communication method of claim 5, further comprising the following step:

where there are two or more processors or equipments B, while performing format conversion upon data received from the processor or equipment B, the FPGA/CPLD adds a channel flag bit to each frame of data to indicate communication channel.

8. The communication method of claim 5, further comprising the following step:

where there are two or more processors or equipments B, the processor A adds a channel flag bit to the transmitted data so as to indicate the communication channel.

9. The communication method of claim 7, further comprising the following step:

the processor A identifies the corresponding processor or equipment B transmitting the data according to the channel flag bit added to the received data.

10. The communication method of claim 8, further comprising the following step:

the FPGA/CPLD module forwards data to the corresponding processor or equipment B according to the channel flag bit.

11. A communication method for an embedded system, comprising data transmitting from a processor A to a processor or equipment B, which transmitting particularly comprises the following steps:

a FPGA/CPLD module receives data transmitted from the processor A upon recognition that a frame synchronization signal is transmitted from the processor A; and

the FPGA/CPLD module identifies a data packet according to a protocol A′

agreed upon with the processor A, and forwards the data to the processor or equipment B according to a protocol B′

agreed upon with the processor or equipment B.

12. The communication method of claim 11, further comprising data transmitting from the processor or equipment B to the processor A, which particularly comprises the following steps:

the FPGA/CPLD module receives data transmitted from the processor or equipment B; and

the FPGA/CPLD module identifies the data packet according to the protocol B′

agreed upon with the processor or equipment B, and transmits the data to the processor A according to the protocol A′

agreed upon with the processor A.

13. The communication method of claim 11, further comprising the following steps:

when the processor A is transmitting data, a channel flag bit indicating a targeted processor or equipment B is written into the data; and

when forwarding the data, the FPGA/CPLD module forwards the data to the corresponding processor or equipment B according to identification of the channel flag bit added to the data.

14. The communication method of claim 12, further comprising the following steps:

when forwarding the data, the FPGA/CPLD identifies the channel flag bit of the processor or equipment B and correspondingly adds the same to the data, which is then forwarded to the processor A; and

the processor A then identifies the data transmitting party according to the channel flag bit.