Early Notification of Error Via Software Interrupt and Shared Memory Write

• US 20080126651A1
• Filed: 09/12/2006
• Published: 05/29/2008
• Est. Priority Date: 09/12/2006
• Status: Active Grant

• Current Assignee: Twitter Inc (X Holdings Corp.)
• Original Assignee: International Business Machines Corporation
• Inventors: Chen, Chiahong, Blinick, Stephen LaRoux, Brewer, Scott Alan, Andre, Herve Gilbert Philippe
• Granted Patent: US 7,685,476 B2
• Time in Patent Office: Days
• US Class Current: 710/267
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/2089 Redundant storage control functionality

Abstract

A method of providing error notification in a storage subsystem includes writing a first defined value by a host adapter of the storage subsystem to a system management interrupt (SMI) register to generate a hardware interrupt, registering and handling the hardware interrupt by a kernel module of the storage subsystem, writing a second defined value to a shared memory location of the storage subsystem by the kernel module, and reading a shared memory offset value by the host adapter. A system for providing error notification in a storage subsystem includes a controller including a serial management interface (SMI) register subcomponent, a first processing component connected to the controller having a kernel module, and a second processing component connected to the controller executing host adapter software.

Claims

1. A method of providing error notification in a storage subsystem, comprising:

writing a first defined value to a system management interrupt (SMI) register to generate a hardware interrupt;

registering and handling the hardware interrupt by a kernel module of the storage subsystem;

writing a second defined value to a shared memory location of the storage subsystem by the kernel module; and

reading a shared memory offset location by a host adapter of the storage subsystem.

2. The method of claim 1, wherein writing a first defined value occurs subsequent to a predetermined passage of time having an accompanying lack of mail communication from a processing component of the storage subsystem.

3. The method of claim 1, wherein the SMI register is located in a processing component of the storage subsystem.

4. The method of claim 3, wherein the processing component further comprises a processor bridge.

5. The method of claim 1, wherein writing a first defined value to SMI register is performed subsequent to a determination by the storage subsystem of a lack of peripheral component interconnect (PCI) mail for a predetermined period of time.

6. The method of claim 1, wherein if the shared memory offset location read by the host adapter differs from the second defined value, the host adapter disconnects from a host.

7. A system for providing error notification in a storage subsystem, comprising:

a controller including a system management interrupt (SMI) register subcomponent;

a first processing component connected to the controller, the first processing component including a kernel module; and

a second processing component connected to the controller, the second processing component executing host adapter software, wherein upon an absence of peripheral component interconnect (PCI) mail communication from the first processing component over a predefined period of time;

the controller writes a first defined value to the SMI register to generate a hardware interrupt, and

the kernel module registers the hardware interrupt and writes a second defined value to a shared memory location of the storage subsystem.

8. The system of claim 7, wherein subsequent to the kernel module writing the second defined value, a shared memory offset value is read by a host adapter.

9. The system of claim 7, wherein the controller further includes memory controller and/or PCI bridge subcomponents.

10. The system of claim 9, wherein the controller further comprises a processor bridge.

11. The system of claim 8, wherein if the shared memory offset value differs from the second defined value, the host adapter disconnects from a host.

12. A method of providing error notification in a computer system, comprising:

determining a system event characterized by a lack of peripheral component interconnect (PCI) mail emanating from a processing subcomponent of the computer system over a predetermined period of time;

generating a first defined value upon the system event by a host adapter of the computer system, the first defined value written to a system management interrupt (SMI) register to cause a hardware interrupt;

registering the hardware interrupt using a kernel module located in the processing subcomponent;

writing a second defined value to a shared memory location of the computer system; and

reading a shared memory offset value by the host adapter of the computer system, wherein if the shared memory offset value differs from the second defined value, the host adapter disconnects from a host.

13. The method of claim 12, wherein the SMI register is located in a controller device of the computer system.

14. The method of claim 13 wherein the controller device further performs memory controller and/or PCI bridge functions.

15. The method of claim 14, wherein the controller device further comprises a processor bridge.