Non-volatile memory system storing data in single-level cell or multi-level cell according to data characteristics

• US 20080126680A1
• Filed: 12/18/2006
• Published: 05/29/2008
• Est. Priority Date: 11/03/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Chan-ik, Talawar, Prakash, Lee, Yang-sup
• Granted Patent: US 7,676,626 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0643 Management of files
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 Hybrid storage device
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Provided is a system storing data received from an application or file system in a non-volatile memory system of single-level cells and multi-level cells in accordance with one or more data characteristics.

Claims

1. In a system storing write data received from at least one of an application and a file system in a non-volatile memory system, the non-volatile memory system comprises:

a non-volatile memory cell array having a plurality of multi-level cells forming a MLC area and a plurality of single-level cells forming a SLC area;

an interface unit analyzing a characteristic of the write data and generating a corresponding data characteristic signal; and

a flash transition layer determining whether the write data should be stored in the MLC area or the SLC area on the basis of the data characteristic signal.

2. The system of claim 1, wherein the interface unit is located on the same abstraction layer on which the application or the file system is located.

3. The system of claim 1, wherein the interface unit is located on a different abstraction layer than the flash transition layer.

4. The system of claim 1, wherein the interface unit comprises:

a file system interface that analyzes the characteristic of write data received from the file system and communicates a corresponding data characteristic signal to the flash transition layer.

5. The system of claim 4, wherein

the data characteristic signal indicates that the write data is accessed by the file system;

and

the flash transition layer comprises a hybrid algorithm unit that determines in response to the data characteristic signal that the write data should be written to SLC area or MLC area.

6. The system of claim 4, wherein the file system interface determines whether an address associated with the write data corresponds to at least one of a FAT region or meta data region of an external memory and communicates a corresponding data characteristic signal to the flash transition layer.

7. The system of claim 1, wherein the interface unit comprises:

an application interface that determines whether an address associated with write data received from the application is frequently updated and communicates a corresponding data characteristic signal to the flash transition layer.

8. The system of claim 7, wherein the flash transition layer comprises a hybrid algorithm unit that determines that the write data should be written to the SLC area or the MLC area on the basis of the data characteristic signal.

9. The system of claim 1, wherein the flash transition layer comprises a mapping unit capable of mapping an address for the write data into a physical address for the non-volatile memory cell array.

10. In a system storing write data received from a host in a non-volatile memory system, the non-volatile memory system comprises:

a non-volatile memory cell array having a plurality of multi-level cells forming a MLC area and a plurality of single-level cells forming a SLC area;

an interface unit analyzing a characteristic of the write data received from the host and generating a corresponding data characteristic signal; and

a flash transition layer determining whether the write data should be stored in the MLC area or the SLC area on the basis of the data characteristic signal,

wherein the interface unit is located on the same abstraction layer on which the host is located.

11. The system of claim 10, wherein the interface unit is located on a different abstraction layer than the flash transition layer.

13. The system of claim 11, wherein the flash transition layer further comprises:

a data block history storage unit including a plurality of entries;

each entry comprising a data block number identifying a corresponding data block, a count value indicating a number of times the corresponding data block has been accessed by the system, and a least recently used value.

15. The system of claim 11, wherein the file system aware unit determines whether the address associated with the write data corresponds to an address in at least one of a FAT region and a meta data region of an external memory.

16. The system of claim 11, wherein the hybrid algorithm unit determines that write data received from the file system should be written to the SLC area when the write data will be accessed by the file system, and further determines that the write data should be written to the MLC area when the write data will not accessed by the file system.

17. The system of claim 11, wherein the hybrid algorithm unit determines that write data received from the application should be written to the SLC area when an address associated with the write data is frequently updated, and further determines that the write data should be written to the MLC area when the address associated with the write data is not frequently updated.

12. In a system storing write data received from at least one of an application and a file system in a non-volatile memory system, the non-volatile memory system comprises:

a non-volatile memory cell array having a plurality of multi-level cells forming a MLC area and a plurality of single-level cells forming a SLC area; and

a flash transition layer,

the flash transition layer comprises;

a file system aware unit determining whether write data received from the file system is accessed by the file system and generating a corresponding data characteristic signal;

an application aware unit determining whether an address associated with write data received from the application is frequently updated and generating a corresponding data characteristic signal; and

a hybrid algorithm unit determining whether the write data received respectively from the application and the file system should be written to the MLC area or the SLC area on the basis of either data characteristic signal generated by the file system aware unit and the application ware unit.

14. The system of claim 12, wherein the application aware unit determines whether the address associated with of the write indicates frequently updated data with reference to the data block history storage unit.

18. The non-volatile memory system of claim 12, wherein the flash transition layer further comprises a mapping unit capable of mapping an address associated with the write data into a physical address for the non-volatile memory cell array.