CACHING METHOD FOR NAND FLASH TRANSLATION LAYER
First Claim
1. A caching method for NAND flash translation layer, comprising the following steps:
- (A) starting;
(B) establishing a caching mechanism for the address translation between a flash memory'"'"'s logical and physical addresses;
(C) establishing a search tree in the caching mechanism;
(D) establishing a plurality of internal and external translation nodes in the search tree;
(E) pointing the external translation nodes to link list of translation units, respectively, wherein each translation unit specifies a range of consecutive flash memory physical addresses corresponding to a range of consecutive logical addresses, a number of translation units are connected into a link list, and an external translation node points to the link list;
(F) For a target logical address, determining if a translation unit having a range of logical addresses covers the target logical address is found by traversing the search tree from the root and, if yes, obtaining the corresponding flash memory physical address using the translation unit;
(G) determining whether the access is a read or write operation and, if it is a read operation, continuing to step (H);
otherwise, continuing to step (I);
(H) conducting a read access caching operation based on the determined physical address and continuing to step (J);
(I) conducting a write access caching operation based on the determined physical address; and
(J) ending.
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Accused Products
Abstract
A caching method provides a cashing mechanism between a logical addresses and a flash memory physical addresses. The cashing mechanism involves a search tree which contains a number of internal and external translation nodes. Each external translation node points to a link list of translation units, and each translation unit records a range of logical addresses and the corresponding range of physical addresses, in addition to a version value. By traversing the search tree to reach a translation unit, the physical address of a target logical address can be determined in an efficient manner. The version value of the translation unit can be used to determine the space taken up for storing the mapping of the logical and physical addresses should be released for reuse.
22 Citations
17 Claims
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1. A caching method for NAND flash translation layer, comprising the following steps:
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(A) starting; (B) establishing a caching mechanism for the address translation between a flash memory'"'"'s logical and physical addresses; (C) establishing a search tree in the caching mechanism; (D) establishing a plurality of internal and external translation nodes in the search tree; (E) pointing the external translation nodes to link list of translation units, respectively, wherein each translation unit specifies a range of consecutive flash memory physical addresses corresponding to a range of consecutive logical addresses, a number of translation units are connected into a link list, and an external translation node points to the link list; (F) For a target logical address, determining if a translation unit having a range of logical addresses covers the target logical address is found by traversing the search tree from the root and, if yes, obtaining the corresponding flash memory physical address using the translation unit; (G) determining whether the access is a read or write operation and, if it is a read operation, continuing to step (H);
otherwise, continuing to step (I);(H) conducting a read access caching operation based on the determined physical address and continuing to step (J); (I) conducting a write access caching operation based on the determined physical address; and (J) ending. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification