MEMORY POWER AND PERFORMANCE MANAGEMENT

• US 20080126686A1
• Filed: 11/27/2007
• Published: 05/29/2008
• Est. Priority Date: 11/28/2006
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Shalvi, Ofir, Sokolov, Dotan
• Granted Patent: US 7,924,648 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for storage includes collecting information regarding respective performance characteristics of a plurality of memory units in a memory array, each memory unit including one or more cells of the memory array. When data are received for storage in the memory array, a memory unit is selected responsively to the respective performance characteristics, and the received data are stored in the selected memory unit.

Claims

1. A method for storage, comprising:

collecting information regarding respective performance characteristics of a plurality of memory units in a memory array, each memory unit comprising one or more cells of the memory array;

receiving data for storage in the memory array;

selecting a memory unit responsively to the respective performance characteristics; and

storing the received data in the selected memory unit.

2. The method according to claim 1, wherein the performance characteristics comprise a power consumption characteristic.

3. The method according to claim 2, wherein selecting the memory unit comprises receiving an indication that the memory array is to operate in a power-saving mode, and selecting the memory unit responsively to the indication.

4. The method according to claim 3, wherein receiving the indication comprises sensing whether an electronic device in which the memory array is installed is connected to an external power source, and invoking the power-saving mode when the external power source is disconnected.

5. The method according to claim 3, wherein storing the received data comprises writing the data to the selected memory unit in accordance with write parameters responsive to the power-saving mode.

6. The method according to claim 2, wherein the power consumption characteristic comprises a maximum voltage value for writing the data to the cells in each memory unit.

7. The method according to claim 2, wherein the power consumption characteristic is selected from a group of characteristics consisting of a number of program-and-verify iterations required to program the cells in each memory unit, a sensing time of the cells in each memory unit, and an amount of pre-processing required to prepare the data for storage in the cells in each memory unit.

8. The method according to claim 1, wherein collecting the information comprises storing the information in a record accessible to a memory controller in an electronic device in which the memory array is installed, wherein the memory controller receives the data for storage from a host processor in the electronic device, and wherein selecting the memory unit comprises accessing the record using the memory controller.

9. The method according to claim 8, wherein collecting the information comprises evaluating the performance characteristics of the memory units before installation of the memory array in the electronic device.

10. The method according to claim 8, wherein collecting the information comprises evaluating the performance characteristics of the memory units after the memory array has been installed in the electronic device.

11. The method according to claim 10, wherein the performance characteristics are measured and stored in the record by the memory controller.

12. The method according to claim 1, wherein the performance characteristics comprise at least one performance characteristic selected from a group of the performance characteristics consisting of signal characteristics and speed characteristics.

13. A method for storage, comprising:

receiving data from a host processor for storage by a memory controller in a memory array;

receiving an input at the memory controller indicating that the memory controller is to operate in a power-saving mode; and

writing the data from the memory controller to the memory array in accordance with write parameters appropriate to the power-saving mode.

14. The method according to claim 13, wherein receiving the input comprises sensing whether an electronic device in which the memory array is installed is connected to an external power source, and invoking the power-saving mode when the external power source is disconnected.

15. The method according to claim 13, wherein the memory array comprises cells that are capable of storing a first number of bits per cell, and wherein writing the data comprises, while the memory controller is operating in the power-saving mode, programming the cells with a second number of bits per cell, which is less than the first number.

16. The method according to claim 15, and comprising copying the data when the memory controller is operating in a full-power mode so as to store the data at the first number of bits per cell.

17. The method according to claim 13, wherein writing the data comprises applying a pre-processing algorithm to the data before programming the cells, and modifying a strength of the pre-processing algorithm responsively to the input.

18. The method according to claim 17, wherein applying the pre-processing algorithm comprises encoding the data for storage using an error-correcting code having a given code strength while the memory controller is operating in a full-power mode, and wherein modifying the strength comprises reducing the code strength that is applied to the data for storage while the memory controller is operating in the power-saving mode.

19. The method according to claim 17, wherein applying the pre-processing algorithm comprises compressing the data for storage, and wherein modifying the strength comprises reducing the strength of compression that is applied to the data for storage while the memory controller is operating in the power-saving mode.

20. The method according to claim 13, wherein the data are written to the memory array using incremental-step pulse programming (ISPP) increments of a given size while the memory controller is operating in a full-power mode, and wherein writing the data comprises modifying the size of the ISPP increments that are used to write the data to the memory array while the memory controller is operating in the power-saving mode.

21. The method according to claim 13, wherein writing the data comprises programming the memory array while the memory controller is operating in a full-power mode so as to reduce an amount of power consumed in subsequently reading the data from the memory array while the memory controller is operating in the power-saving mode.

22. The method according to claim 21, wherein programming the memory array comprises selecting cells of the memory array having low-power read characteristics, and writing the data to the selected cells.

23. The method according to claim 21, wherein programming the memory array comprises writing the data to cells of the memory array having a given wear level, and encoding the data for storage in the cells using a code selected responsively to the wear level.

24. The method according to claim 21, wherein programming the memory array comprises writing the data to cells of the memory array having a given level of error, and encoding the data for storage in the cells using a code selected responsively to the level of the error.

25. A method for storage, comprising:

receiving an instruction from a host processor to a memory controller to transfer data between a buffer and a memory array;

receiving an input at the memory controller indicating that the memory controller is to operate in a high-throughput mode; and

transferring the data between the buffer and the memory array using the memory controller at a throughput rate appropriate to the high-throughput mode.

26. The method according to claim 25, wherein receiving the input comprises instructing the memory controller to write data from the buffer to the memory array in the high-throughput mode upon determining that the buffer is about to overflow.

27. The method according to claim 25, wherein receiving the input comprises instructing the memory controller to read data from the memory array to the buffer in the high-throughput mode upon determining that the buffer is nearly empty.

28. Storage apparatus, comprising:

a memory, which is configured to store a record of respective performance characteristics of a plurality of memory units in a memory array, each memory unit comprising one or more cells of the memory array; and

a memory controller, which is coupled to receive data for storage in the memory array, and to select a memory unit responsively to the respective performance characteristics, and to store the received data in the selected memory unit.

29. The apparatus according to claim 28, wherein the performance characteristics comprise a power consumption characteristic.

30. The apparatus according to claim 29, wherein the memory controller is coupled to receive an indication that the memory is to operate in a power-saving mode, and to select the memory unit responsively to the indication.

31. The apparatus according to claim 29, wherein the power consumption characteristic comprises a maximum voltage value for writing the data to the cells in each memory unit.

32. The apparatus according to claim 28, wherein the memory controller and the memory array are installed in an electronic device, which comprises a host processor that passes the data to the memory controller for storage in the memory array.

33. The apparatus according to claim 28, wherein the performance characteristics comprise at least one performance characteristic selected from a group of the performance characteristics consisting of signal characteristics and speed characteristics.

34. Storage apparatus, comprising a memory controller, which is configured to receive data from a host processor for storage by the memory controller in a memory array, wherein the memory controller comprises an input for receiving an indication that the memory controller is to operate in a power-saving mode and is configured, in response to the indication, to write the data to the memory array in accordance with write parameters appropriate to the power-saving mode.

35. The apparatus according to claim 34, wherein the memory controller is configured to sense, via the input, whether an electronic device in which the memory is installed is connected to an external power source, and to invoke the power-saving mode when the external power source is disconnected.

36. The apparatus according to claim 34, wherein the memory array includes cells that are capable of storing a first number of bits per cell, and wherein the memory controller is configured, while operating in the power-saving mode, to program the cells with a second number of bits per cell, which is less than the first number.

37. The apparatus according to claim 36, wherein the memory controller is configured, while operating in a full-power mode, to copy the data to the memory array at the first number of bits per cell.

38. The apparatus according to claim 34, wherein the memory controller is configured to apply a pre-processing algorithm to the data before programming the cells, and to modify a strength of the pre-processing algorithm responsively to the indication.

39. The apparatus according to claim 34, wherein the memory controller is configured, while operating in a full-power mode, to write the data to the memory array using incremental-step pulse programming (ISPP) increments of a given size, and to modify the size of the ISPP increments that are used to write the data to the memory while the memory controller is operating in the power-saving mode.

40. The apparatus according to claim 34, wherein the memory controller is configured to program the memory array while the memory controller is operating in a full-power mode so as to reduce an amount of power consumed in reading the data from the memory array while the memory controller is operating in the power-saving mode.

41. Storage apparatus, comprising:

a memory array comprising a plurality of memory cells, which are arranged in memory units, each memory unit comprising one or more of the cells of the memory array and having respective performance characteristics; and

a memory controller, which is coupled to receive data for storage in the memory array, and to select a memory unit responsively to the respective performance characteristics of the memory unit, and to store the received data in the selected memory unit.

42. Storage apparatus, comprising:

a memory array comprising a plurality of memory cells; and

a memory controller, which is configured to receive data from a host processor and to receive an input indicating that the storage device is to operate in a power-saving mode, and to write the data to the memory array in accordance with write parameters appropriate to the power-saving mode.