Memory module with memory stack

• US 20080126690A1
• Filed: 02/05/2007
• Published: 05/29/2008
• Est. Priority Date: 02/09/2006
• Status: Abandoned Application

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google LLC (Alphabet Inc.)
• Inventors: Weber, Frederick Daniel, Rajan, Suresh N.
• Application Number:
  US11/702,960
• Publication Number:
  US 20080126690A1
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G11C 11/00 Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor G11C14/00 - G11C21/00 take precedence
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array

Abstract

A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, an interface circuit maps virtual addresses from the host system to physical addresses of the DRAM integrated circuits in a linear manner. In a further embodiment, the interface circuit maps one or more banks of virtual addresses from the host system to a single one of the DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system. In still other embodiments, the buffer circuit interfaces the memory stack to the host system for configuring one or more of the DRAM integrated circuits in the memory stack. Neither the patentee nor the USPTO intends for details set forth in the abstract to constitute limitations to claims not explicitly reciting those details.

Claims

1. A memory module comprising:

at least one memory stack that comprises a plurality of DRAM integrated circuits; and

interface circuit, coupled to a host system, for interfacing said memory stack to said host system so to operate said memory stack as a single DRAM integrated circuit.

2. The memory module as set forth in claim 1, wherein said interface circuit comprises a buffer integrated circuit incorporated as part of said memory stack.

3. The memory module as set forth in claim 1, wherein said memory module comprises an un-buffered DIMM.

4. The memory module as set forth in claim 1, wherein said memory module comprises a registered DIMM.

5. The memory module as set forth in claim 1, wherein said memory module comprises a SO-DIMM.

6. The memory module as set forth in claim 1, wherein said memory module comprises a FB-DIMM.

7. The memory module as set forth in claim 1, further comprising:

a raw card;

said memory module electrically coupled to said raw card; and

one or more electrical circuits electrically coupled to said raw card, said one or more electrical circuits buried at least partially beneath a plane defining a first primary surface of said raw card.

8. A memory module comprising:

at least one memory stack that comprises a plurality of DRAM integrated circuits; and

buffer integrated circuit, coupled to a host system, for interfacing said memory stack to said host system so to operate said memory stack as at least two DRAM integrated circuits.

9. The memory module as set forth in claim 8, wherein said buffer integrated circuit further for interfacing said memory stack to said host system so to operate said memory stack as at least two ranks of DRAM integrated circuits.

10. The memory module as set forth in claim 8, wherein said memory stack comprises a buffer and a plurality of DRAM integrated circuits.

11. The memory module as set forth in claim 8, further comprising:

a first printed circuit board for mounting said ranks of DRAM integrated circuits; and

a second printed circuit board comprising at least one additional memory stack, coupled to said memory by means of a connector or interposer.

12. The memory module as set forth in claim 11, wherein:

said second printed circuit board comprises a DIMM with said interposer located on a front side of said DIMM.

13. The memory module as set forth in claim 11, wherein:

said second printed circuit board comprises a DIMM with said interposer located on a back side of said DIMM.

14. The memory module as set forth in claim 8, wherein said memory stack further comprises at least one non-volatile memory integrated circuit.

15. The memory module as set forth in claim 8, wherein said buffer integrated circuit further for operating two DDR2 SDRAM integrated circuits in parallel so as appear as a single DDR3 SDRAM integrated circuit to the host system.

16. The memory module as set forth in claim 8, wherein one or more layers of said memory stack further comprises at least one decoupling capacitor.

17. A computer system comprising:

a memory controller; and

at least one memory module comprising;

at least one memory stack that comprises a plurality of DRAM integrated circuits; and

interface circuit, coupled to said memory controller, for interfacing said memory stack to said memory controller so to operate said memory stack as a single DRAM integrated circuit.

18. The computer system as set forth in claim 17, wherein said DRAM integrated circuits of said memory module further comprising a ganged configuration for RAID memory.

19. The computer system as set forth in claim 17, wherein said DRAM integrated circuits of said memory module further comprising a configuration for distributed power dissipation.

20. The computer system as set forth in claim 17, wherein one or more of said DRAM integrated circuits in said stack of said memory module comprises a device for measuring ambient temperature of said memory module.

21. The computer system as set forth in claim 17, wherein one or more of said DRAM integrated circuits in said stack of said memory module comprises a capacitor.

22. The computer system as set forth in claim 17, wherein one or more of said DRAM integrated circuits in said stack of said memory module comprises a plurality of power and ground pins.

23. A computer system comprising:

a memory controller; and

at least one memory module comprising;

at least one memory stack that comprises a plurality of DRAM integrated circuits; and

buffer integrated circuit, coupled to a host said memory controller, for interfacing said memory stack to said memory controller so to operate said memory stack as at least two DRAM integrated circuits.

24. A memory module comprising:

at least one memory stack that comprises a plurality of DRAM integrated circuits; and

interface circuit, coupled to a host system, for mapping virtual addresses from said host system to physical addresses of said DRAM integrated circuits in a linear manner.

25. The memory module as set forth in claim 24, wherein:

said physical addresses identify at least one physical bank; and

said interface circuit for mapping a physical bank to a different one of said DRAM integrated circuits.

26. A memory module comprising:

at least one memory stack that comprises a plurality of DRAM integrated circuits; and

interface circuit, coupled to a host system, for mapping one or more banks of virtual addresses from said host system to a single one of said DRAM integrated circuits.

27. A printed circuit motherboard comprising:

at least one memory stack that comprises a plurality of DRAM integrated circuits; and

interface circuit, coupled to a host system, for interfacing said memory stack to said host system so to operate said memory stack as a single DRAM integrated circuit.

28. The printed circuit motherboard as set forth in claim 27, wherein said interface circuit comprises a buffer integrated circuit incorporated as part of said memory stack.

29. The printed circuit motherboard as set forth in claim 27, wherein said printed circuit motherboard comprises an un-buffered DIMM.

30. The printed circuit motherboard as set forth in claim 27, wherein said printed circuit motherboard comprises a registered DIMM.

31. The printed circuit motherboard as set forth in claim 27, wherein said printed circuit motherboard comprises a SO-DIMM.

32. The printed circuit motherboard as set forth in claim 27, wherein said printed circuit motherboard comprises a FB-DIMM.