Methods and Arrangements for Hybrid Data Storage

• US 20080126716A1
• Filed: 11/02/2006
• Published: 05/29/2008
• Est. Priority Date: 11/02/2006
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Daniels, Scott L.
• Granted Patent: US 7,584,335 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 2212/306 In system interconnect, e.g. between two buses

Abstract

Methods and arrangements for hybrid data storage are described herein. Embodiments may comprise a hybrid memory controller to facilitate accesses of more than on type of memory device, referred to generally hereafter as a hybrid memory device or hybrid cache device. The hybrid memory controller may include split logic to determine whether to split data of a write request into more than one portion and to store each portion in a different type of data storage device. For example, one embodiment comprises a hybrid memory controller to store data in both SRAM and DRAM devices. The SRAM and DRAM devices may include distinct circuits on a die, distinct dies within a chip, distinct chips on a memory module, distinct memory modules, or the like.

Claims

1. A method to store data in memory, the method comprising:

identifying, by a memory controller, a first portion of the data associated with a write request;

storing, by the memory controller, the first portion of the data in a first memory device; and

storing, by the memory controller, a second portion of the data in a second memory device, the first memory device having an initial access latency that is shorter than an initial access latency of the second memory device, wherein memory locations of the first portion and the second portion have consecutive memory addresses.

2. The method of claim 1, further comprising assigning the consecutive memory addresses as logical memory addresses for the memory locations of the first portion and the second portion of the data.

3. The method of claim 1, further comprising:

receiving a read request for the data;

accessing, by the memory controller, the first memory device to retrieve the first portion of the data;

accessing, by the memory controller, the second memory device to retrieve a second portion of the data during the accessing of the first memory device; and

transmitting the first and second portions of the data in response to the read request.

4. The method of claim 1, further comprising determining that the data of the write request is suitable for division into the first and second portions.

5. The method of claim 1, wherein identifying the first portion comprises identifying an amount of the data to store in the first memory device to substantially hide the initial latency of the responding with the second portion of the data from the second memory device.

6. The method of claim 1, wherein storing the first portion of the data comprises storing the first portion in a first chip, wherein storing the second portion comprises storing the second portion in a second chip.

7. The method of claim 1, wherein storing the first portion of the data comprises transmitting the first portion to a first queue for storage in static random access memory and storing the second portion of the data comprises transmitting the second portion to a second queue for storage in dynamic random access memory.

8. An apparatus to store data, the apparatus comprising:

a first type of memory device;

a second type of memory device; and

a memory controller coupled with the first type of memory device and the second type of memory device, the memory controller to be responsive to a write request to write data associated with the write request to the first type of memory device and the second type of memory device and responsive to a read request for the data to read a first portion of the data from the first type of memory device during an initial latency associated with access to a second portion of the data in the second type of memory device, wherein memory locations for the first portion of the data and the second portion of the data are assigned consecutive memory addresses.

9. The apparatus of claim 8, wherein the first type of memory device comprises a static random access memory (SRAM) device and the second type of memory device comprises a dynamic random access memory (DRAM) device.

10. The apparatus of claim 8, wherein the first type of memory device and the second type of memory device comprise interleaved memory banks on a die.

11. The apparatus of claim 8, wherein memory controller comprises selection logic to identify the first portion of the data to store in the first type of memory device.

12. The apparatus of claim 8, wherein the memory controller comprises selection logic to determine whether to store the first portion of the data in the first type of memory device.

13. The apparatus of claim 12, wherein the selection logic comprises logic to determine to store the first portion of the data in the first type of memory device based upon a priority associated with the data.

14. A system for hybrid memory storage, the system comprising:

a processor;

a static random access memory (SRAM) device;

a dynamic random access memory (DRAM) device; and

a memory controller coupled with the processor via a bus to store data of a write request from the processor in the SRAM and DRAM devices, wherein the memory controller comprises logic to split the data into at least a first portion to store in the SRAM device and a second portion to store in the DRAM device, memory locations of the first portion and the second portion to have consecutive memory addresses.

15. The system of claim 14, wherein the SRAM device and the DRAM device are mounted on a memory module.

16. The system of claim 14, wherein the SRAM device comprises a first memory module and the DRAM device comprises a different memory module.

17. The system of claim 14, wherein the memory controller comprises a first memory controller to access the SRAM device and a second memory controller to access the DRAM device.

18. A device comprising:

a first memory device with a low initial access latency;

a second memory device with a high initial access latency; and

address-decoding logic interconnected with the first memory device and the second memory device, the address-decoding logic to associate a first, consecutive physical address range with the first memory device and a second, consecutive physical address range with the second memory device, wherein the first, consecutive physical address range is consecutive with the second, consecutive physical address range.

19. The device of claim 18, wherein the first memory device comprises a bank of SRAM and the second memory device comprises one or more banks of DRAM.

20. The device of claim 18, wherein the first memory device comprises a first die and the second memory device comprises a second die.