Methods and Arrangements for Hybrid Data Storage
First Claim
1. A method to store data in memory, the method comprising:
- identifying, by a memory controller, a first portion of the data associated with a write request;
storing, by the memory controller, the first portion of the data in a first memory device; and
storing, by the memory controller, a second portion of the data in a second memory device, the first memory device having an initial access latency that is shorter than an initial access latency of the second memory device, wherein memory locations of the first portion and the second portion have consecutive memory addresses.
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Abstract
Methods and arrangements for hybrid data storage are described herein. Embodiments may comprise a hybrid memory controller to facilitate accesses of more than on type of memory device, referred to generally hereafter as a hybrid memory device or hybrid cache device. The hybrid memory controller may include split logic to determine whether to split data of a write request into more than one portion and to store each portion in a different type of data storage device. For example, one embodiment comprises a hybrid memory controller to store data in both SRAM and DRAM devices. The SRAM and DRAM devices may include distinct circuits on a die, distinct dies within a chip, distinct chips on a memory module, distinct memory modules, or the like.
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Citations
20 Claims
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1. A method to store data in memory, the method comprising:
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identifying, by a memory controller, a first portion of the data associated with a write request; storing, by the memory controller, the first portion of the data in a first memory device; and storing, by the memory controller, a second portion of the data in a second memory device, the first memory device having an initial access latency that is shorter than an initial access latency of the second memory device, wherein memory locations of the first portion and the second portion have consecutive memory addresses. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An apparatus to store data, the apparatus comprising:
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a first type of memory device; a second type of memory device; and a memory controller coupled with the first type of memory device and the second type of memory device, the memory controller to be responsive to a write request to write data associated with the write request to the first type of memory device and the second type of memory device and responsive to a read request for the data to read a first portion of the data from the first type of memory device during an initial latency associated with access to a second portion of the data in the second type of memory device, wherein memory locations for the first portion of the data and the second portion of the data are assigned consecutive memory addresses. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A system for hybrid memory storage, the system comprising:
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a processor; a static random access memory (SRAM) device; a dynamic random access memory (DRAM) device; and a memory controller coupled with the processor via a bus to store data of a write request from the processor in the SRAM and DRAM devices, wherein the memory controller comprises logic to split the data into at least a first portion to store in the SRAM device and a second portion to store in the DRAM device, memory locations of the first portion and the second portion to have consecutive memory addresses. - View Dependent Claims (15, 16, 17)
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18. A device comprising:
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a first memory device with a low initial access latency; a second memory device with a high initial access latency; and address-decoding logic interconnected with the first memory device and the second memory device, the address-decoding logic to associate a first, consecutive physical address range with the first memory device and a second, consecutive physical address range with the second memory device, wherein the first, consecutive physical address range is consecutive with the second, consecutive physical address range. - View Dependent Claims (19, 20)
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Specification