SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR DELAYING AN OPERATION THAT REDUCES A LIFETIME OF MEMORY

• US 20080126719A1
• Filed: 09/07/2007
• Published: 05/29/2008
• Est. Priority Date: 11/24/2006
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: SandForce, Inc. (Broadcom, Inc.)
• Inventors: Danilak, Radoslav
• Granted Patent: US 7,809,900 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement

Abstract

A system, method, and computer program product are provided for delaying operations that reduce a lifetime of memory. In use, at least one aspect associated with a lifetime of memory is identified. To this end, at least one operation that reduces the lifetime of the memory is delayed, based on the aspect.

Claims

1. A method, comprising:

identifying at least one aspect associated with a lifetime of memory; and

delaying at least one operation that reduces the lifetime of the memory, based on the aspect.

2. The method of claim 1, wherein the lifetime includes at least one of a desired lifetime, an actual lifetime, and an estimated lifetime.

4. The method of claim 1, wherein the operation is delayed by delaying a command that initiates the operation.

5. The method of claim 1, wherein the delaying is further based on an application that initiates the operation.

6. The method of claim 1, wherein the delaying is independent of an application that initiates the operation.

7. The method of claim 1, wherein the operation includes an erase operation.

8. The method of claim 1, wherein the operation includes a program operation.

9. The method of claim 1, wherein the operation is delayed if a desired lifetime duration exceeds an estimated lifetime duration.

10. The method of claim 1, wherein the operation is conditionally delayed based on historical use of the memory.

11. The method of claim 1, wherein the operation is conditionally delayed based on predicted use of the memory.

12. The method of claim 1, wherein the operation is conditionally delayed based on an integral function of use of the memory.

13. The method of claim 1, wherein the operation is conditionally delayed based on a time interval during which the operation is initiated.

14. The method of claim 13, wherein the time interval includes at least one of a time of the day, a day of the week, and a month of the year.

15. The method of claim 1, wherein only a portion of the operation is delayed.

16. The method of claim 1, wherein the memory includes a mechanical storage device.

17. The method of claim 1, wherein the memory includes a non-mechanical storage device.

18. The method of claim 1, wherein the memory includes a volatile memory device.

19. The method of claim 1, wherein the memory includes a nonvolatile memory device.

20. The method of claim 1, wherein the nonvolatile memory device includes at least one of single-bit per cell NOR flash memory, multi-bit per cell NOR flash memory, single-bit per cell NAND flash memory, multi-bit per cell NAND flash memory, multi-level-multi-bit per cell NAND flash, and large block flash memory.

3. The method of claim L wherein the aspect includes at least one of a period of time, a rate of the operations that reduce the lifetime of the memory, a total permitted number of the operations that reduce the lifetime of the memory, and a duration of the lifetime.

21. A computer program product embodied on a computer readable medium, comprising:

computer code for identifying at least one aspect associated with a lifetime of memory; and

computer code for delaying at least one operation that reduces the lifetime of the memory, based on the aspect.

22. An apparatus, comprising:

a controller for delaying at least one operation that reduces a lifetime of a memory, based on at least one aspect associated with the lifetime of the memory.

23. The apparatus of claim 22, wherein the controller is coupled between a system and the memory.

24. The apparatus of claim 22, wherein the controller is coupled, between a system and secondary storage.