Multiple-Core Processor

• US 20080126748A1
• Filed: 09/01/2006
• Published: 05/29/2008
• Est. Priority Date: 09/01/2006
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Shapiro, Michael J., Newhart, Ronald E., Capps, Louis B.
• Application Number:
  US11/469,550
• Publication Number:
  US 20080126748A1
• Time in Patent Office: Days
• US Class Current: 712/30
• CPC Class Codes: G06F 11/2025 using centralised failover control functionality
• CPC Class Codes: G06F 11/2041 with more than one idle spare processing component
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A method, apparatus, and computer program product for using a multi-core integrated circuit to extend the reliability or operating life of an electronic device.

Claims

1. A computer-implemented method of swapping a core in an integrated circuit having multiple cores, the method comprising the steps of:

selecting one or more of the cores for initial operation, wherein at least one remaining core is not operating;

tracking the use of the selected core(s); and

swapping the selected core(s) with the remaining non-selected core(s) after the tracked use has exceeded a predetermined number.

2. The method of claim 1 wherein the step of tracking the use of the selected core(s) includes the step of:

tracking a number of power-on hours that the selected core(s) has been operating.

3. The method of claim 2 wherein the step of swapping the selected core(s) includes the step of:

swapping the selected core(s) with the remaining non-selected core(s) after the tracked number of power-on hours for the selected core(s) exceeds the predetermined number.

4. The method of claim 3 wherein the predetermined number is based on the anticipated number of power-on hours that the selected core(s) will operate without failing.

5. The method of claim 1 wherein the step of tracking the use of the selected core(s) includes the step of:

tracking the number of clock cycles that the selected core(s) has received.

6. The method of claim 5 wherein the step of swapping the selected core(s) includes the step of:

swapping the selected core(s) with the remaining non-selected core(s) after the tracked number of clock cycles for the selected core(s) exceeds the predetermined number.

7. The method of claim 6 wherein the predetermined number is based on the anticipated number of clock cycles that the selected core(s) will operate without failing.

9. The integrated circuit of claim 1 wherein the means for tracking the use of the selected core(s) includes:

means for tracking the number of power-on hours that the selected core(s) has been operating.

10. The apparatus of claim 9 wherein the means for swapping the selected core(s) includes:

means for swapping the selected core(s) with the remaining non-selected core(s) after the tracked number of power-on hours for the selected core(s) exceeds a predetermined number.

8. An apparatus for using multiple cores in an integrated circuit, the apparatus comprising:

means for selecting one or more of the cores for initial operation;

means for tracking the use of the selected core(s); and

means for swapping the selected core(s) with the remaining non-selected core(s) after the tracked use has exceeded a predetermined number.

11. The apparatus of claim 8 wherein the predetermined number is based on the anticipated number of power-on hours that the selected core(s) will operate without failing.

12. The apparatus of claim 8 wherein the means for tracking the use of the selected core(s) includes:

means for tracking the number of clock cycles that the selected core(s) has received.

13. The apparatus of claim 12 wherein the means for swapping the selected core(s) includes:

means for swapping the selected core(s) with the remaining non-selected core(s) after the tracked number of clock cycles for the selected core(s) exceeds a predetermined number.

14. The apparatus of claim 13 wherein the predetermined number is based on the anticipated number of clock cycles that the selected core(s) will operate without failing.

15. A computer program product comprising a computer usable medium having computer usable program code for using multiple cores in an integrated circuit, the computer usable program code comprising:

computer usable program code for selecting one or more of the cores for initial operation;

computer usable program code for tracking the use of the selected core(s); and

computer usable program code for swapping the selected core(s) with the remaining non-selected core(s) after the tracked use has exceeded a predetermined number.

16. The computer program product of claim 15 wherein the computer usable program code for tracking the use of the selected core(s) includes:

computer usable program code for tracking the number of power-on hours that the selected core(s) has been operating.

17. The computer program product of claim 16 wherein the computer usable program code for swapping the selected core(s) includes:

computer usable program code for swapping the selected core(s) with the remaining non-selected core(s) after the tracked number of power-on hours for the selected core(s) exceeds a predetermined number.

18. The computer program product of claim 15 wherein the predetermined number is based on the anticipated number of power-on hours that the selected core(s) will operate without failing.

19. The computer program product of claim 15 wherein the computer usable program code for tracking the use of the selected core(s) includes:

computer usable program code for tracking the number of clock cycles that the selected core(s) has received.

20. The computer program product of claim 19 wherein the computer usable program code for swapping the selected core(s) includes:

computer usable program code for swapping the selected core(s) with the remaining non-selected core(s) after the tracked number of clock cycles for the selected core(s) exceeds a predetermined number.