USING SHARED MEMORY WITH AN EXECUTE-IN-PLACE PROCESSOR AND A CO-PROCESSOR
First Claim
1. A system that facilitates sharing of a memory, comprising:
- a host processor that performs at least one of a data read or data write by accessing the memory via an access channel and generates at least one of a read cycle or write cycle associated with at least one other processor when the host processor wants the at least one other processor to perform a function; and
the at least one other processor that is implemented as a finite state machine and cannot access the memory via the access channel unless the at least one other processor receives the at least one of a read cycle or write cycle from the host processor.
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Accused Products
Abstract
The claimed subject matter provides systems and/or methods that facilitate sharing of a memory, having a single channel of access, between two or more processors. A host processor can be operatively connected to a co-processor and the memory in series. The host processor can execute in place to enable it to execute code directly from the memory, and can arbitrate access to the memory bus and thus the memory, so that the host processor can perform all memory fetches to the memory without interruption by the co-processor. The co-processor can be implemented as a finite state machine, and only accesses the memory during read or write cycles issued by the host processor. Various types of co-processors can be employed to perform various functions, such as cryptography and digital signal processing, for example. The memory can be volatile or non-volatile memory.
24 Citations
20 Claims
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1. A system that facilitates sharing of a memory, comprising:
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a host processor that performs at least one of a data read or data write by accessing the memory via an access channel and generates at least one of a read cycle or write cycle associated with at least one other processor when the host processor wants the at least one other processor to perform a function; and the at least one other processor that is implemented as a finite state machine and cannot access the memory via the access channel unless the at least one other processor receives the at least one of a read cycle or write cycle from the host processor. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A device that facilitates sharing of memory, comprising:
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a host processor that retrieves data by accessing a memory via an access channel and generates a read cycle or write cycle associated with at least one other processor at a time when the host processor wants the at least one other processor to perform an operation; and the at least one other processor that is implemented as a finite state machine and cannot access the memory via the access channel unless the at least one other processor receives the read cycle or write cycle from the host processor. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A method for facilitating access to a memory, having a single access channel, shared by a host processor and at least one other processor, comprising:
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generating at least one of a read or write associated with the host processor; selecting a bypass mode to provide the host processor access to the memory via the single access channel; and retrieving data, associated with the at least one of a read, or write stored in the memory. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification