SCHEDULER HINT METHOD AND SYSTEM TO IMPROVE NETWORK INTERFACE CONTROLLER (NIC) RECEIVE (RX) PROCESSING CACHE PERFORMANCE

• US 20080126751A1
• Filed: 11/27/2007
• Published: 05/29/2008
• Est. Priority Date: 11/27/2006
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Mizrachi, Shay, Tamir, Eliezer
• Application Number:
  US11/945,510
• Publication Number:
  US 20080126751A1
• Time in Patent Office: Days
• US Class Current: 712/30
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions
• CPC Class Codes: G06F 9/485 Task life-cycle, e.g. stopping, restarting, resuming execution G06F9/4881 takes precedence
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: G06F 9/542 Event management; Broadcasting; Multicasting; Notifications
• CPC Class Codes: H04L 49/90 Buffering arrangements

Abstract

Aspects of a scheduler hint method and system to improve network interface controller (NIC) receive (RX) processing cache performance are presented. Aspects of a system may include a NIC that enables generation of a processor selection bias value. The processor selection bias value may comprise hint data. A scheduler within a multiprocessor operating system (OS) executing on a multiprocessor computing system may enable selection of one of a plurality of processors based on the generated processor selection bias value. The scheduler executing on the multiprocessor computer system may enable execution of specified code, for example an egress process task, on the selected one of the plurality of processors. The egress process task may be executing subsequent to an ingress task process, which was executed on the selected one of the plurality of processors in response to one or more data packets received at the NIC.

Claims

1. A method for processing data, the method comprising:

generating a processor selection bias value;

selecting one of a plurality of processors in a multiprocessor computing system based on said generated processor selection bias value; and

executing specified code on said selected one of said plurality of processors.

2. The method according to claim 1, comprising selecting said one of said plurality of processors based on a computed score value.

3. The method according to claim 2, comprising modifying said computed score value based on said generated processor selection bias value.

4. The method according to claim 2, comprising determining said computed score value based on a plurality of scheduler parameters.

5. The method according to claim 4, comprising modify a value for at least a portion of said plurality of scheduler parameters based on said generated processor selection bias value.

6. The method according to claim 4, comprising generating one or more additional scheduler parameters based on said generated processor selection bias value.

7. The method according to claim 6, comprising determining said computed score value based on said plurality of scheduler parameters and said generated one or more additional scheduler parameters.

8. The method according to claim 1, comprising determining a busy status for said selected one of said plurality of processors at a determined time instant.

9. The method according to claim 8, comprising assigning said specified code for execution on said selected one of said plurality processors based on said busy status determination.

10. The method according to claim 9, comprising executing said specified code on said selected one of said plurality of processors following said assigning.

11. The method according to claim 8, comprising assigning, at a subsequent time instant, said specified code for execution on said selected one of said plurality of processors based on said busy status determination.

12. A system for processing data, the system comprising:

one or more circuits that enable generation of a processor selection bias value;

said one or more circuits enable selection of one of a plurality of processors in a multiprocessor computing system based on said generated processor selection bias value; and

said one or more circuits enable execution of specified code on said selected one of said plurality of processors.

13. The system according to claim 12, wherein said one or more circuits enable selection of said one of said plurality of processors based on a computed score value.

14. The system according to claim 13, wherein said one or more circuits enable modification of said computed score value based on said generated processor selection bias value.

15. The system according to claim 13, wherein said one or more circuits enable determination of said computed score value based on a plurality of scheduler parameters.

16. The system according to claim 15, wherein said one or more circuits enable modification of a value for at least a portion of said plurality of scheduler parameters based on said generated processor selection bias value.

17. The system according to claim 15, wherein said one or more circuits enable generation of one or more additional scheduler parameters based on said generated processor selection bias value.

18. The system according to claim 17, wherein said one or more circuits enable determination of said computed score value based on said plurality of scheduler parameters and said generated one or more additional scheduler parameters.

19. The system according to claim 12, wherein said one or more circuits enable determination of a busy status for said selected one of said plurality of processors at a determined time instant.

20. The system according to claim 19, wherein said one or more circuits enable assignment of said specified code for execution on said selected one of said plurality processors based on said busy status determination.

21. The system according to claim 20, wherein said one or more circuits enable execution of said specified code on said selected one of said plurality of processors following said assignment.

22. The system according to claim 19, wherein said one or more circuits enable assignment, at a subsequent time instant, of said specified code for execution on said selected one of said plurality of processors based on said busy status determination.