Contention detection with counter rollover

• US 20080127214A1
• Filed: 10/05/2007
• Published: 05/29/2008
• Est. Priority Date: 10/05/2006
• Status: Abandoned Application

• Current Assignee: John M. Holt
• Original Assignee: John M. Holt
• Inventors: Holt, John M.
• Application Number:
  US11/973,398
• Publication Number:
  US 20080127214A1
• Time in Patent Office: Days
• US Class Current: 719/315
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

In a system such as a multiple computer system where memory locations (A, B, C) can be substantially simultaneously updated from difference sources, an updating count (C, C1) is provided indicative of the sequence of each updating message or signal (195, 295) in a stream of such updating messages or signals. The updating count is stored in a counter. To reduce the storage requirements for the counter and the bandwidth requirements for the updating messages including the count value, small count values are utilized. From time to time sending of updating messages is halted and the count values re-set to avoid arithmetic overflow.

Claims

1. A counter comprising:

at least one finite counter having at least one corresponding memory location;

an interface for receiving updating messages or signals from different external updating message or signal sources, each of which can update said memory locations an updating count value;

a comparison means for comparing sequentially received ones of said updating messages or signals from said different external sources;

said updating messages or signals include a further data bit, which changes state from a first state to a second state if said counter reaches a predetermined maximum count value; and

said comparison means modifies the comparison of sequentially received updating messages or signals in accordance with the states of said further data bit of said sequentially received messages.

2. The counter as in claim 1, further including interrupt means to interrupt the operation of said system from time to time or on the occurrence of a predetermined condition, in order to re-set the count of at least one counter.

3. The counter as in claim 2, further including interrupt means to interrupt the operation of said system from time to time or on the occurrence of a predetermined condition, in order to re-set the value of at least one of said further data bits.

4. The counter as in claim 1, wherein said predetermined condition comprises at least one of said counters approaching or reaching a maximum count value.

5. The counter as in claim 1, wherein the size of said counter is greater than the maximum expected size of any queue of undelivered updating messages.

6. The counter as in claim 1, wherein said comparison means comprises a comparator.

7. A method for counting comprising:

at least one finite counter having at least one corresponding memory location;

receiving updating messages or signals from different external updating message or signal sources, each of which can update said memory locations an updating count value;

comparing sequentially received ones of said updating messages or signals from said different external sources;

altering the state of a further data bit in said updating messages or signals from a first state to a second sate if said counter reaches a predetermined maximum count value; and

modifying the comparison of sequentially received updating messages or signals in accordance with the states of said further data bit of said sequentially received messages.

8. The method for counting as in claim 7, further including interrupting the operation of said counter and/or of an external system coupled with said counter from time to time or on the occurrence of a predetermined condition, in order to re-set the count of at least one counter.

9. The method for counting as in claim 8, further including interrupting the operation of said counter and/or of an external system coupled with said counter from time to time or on the occurrence of a predetermined condition, in order to re-set the value of at least one of said further data bits.

10. The method for counting as in claim 8, wherein said predetermined condition comprises at least one of said counters approaching or reaching a maximum count value.

12. The method for counting as in claim 7, wherein the size of said counter is greater than the maximum expected size of any queue of undelivered updating messages.

11. The method for counting as in claim 89, wherein said predetermined condition comprises at least one of said counters approaching or reaching a maximum count value.

13. In a multiple computer system comprising a plurality of interconnected computing machines, each computing machine having a local memory and a plurality of memory locations, a method comprising:

operating the plurality of computing machines to provide at least a partially replicated shared memory operating environment;

generating a counter value using at least one finite counter, said at least one finite counter having at least one corresponding memory location;

receiving updating messages or signals from different external updating message or signal sources, each of which can update said memory locations an updating count value;

comparing sequentially received ones of said updating messages or signals from said different external sources;

altering the state of a further data bit in said updating messages or signals from a first state to a second sate if said counter reaches a predetermined maximum count value; and

modifying the comparison of sequentially received updating messages or signals in accordance with the states of said further data bit of said sequentially received messages.