Reliability test structure for multilevel interconnect

• US 20080128693A1
• Filed: 03/22/2007
• Published: 06/05/2008
• Est. Priority Date: 11/30/2006
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: Ruan, Wei Wei, Shi, Wen
• Granted Patent: US 8,323,990 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Embodiments in accordance with the present invention relate to structures and methods allowing stress-induced electromigration to be tested in multiple interconnect metallization layers. An embodiment of a testing structure in accordance with the present invention comprises at least two segments of a different metal layer through via structures. Each segment includes nodes configured to receive force and sense voltages. Selective application of force and sense voltages to these nodes allows rapid and precise detection of stress-induced immigration in each of the metal layers.

Claims

1. An interconnect test structure comprising:

a first metallization layer formed on a substrate, the first metallization layer having a first portion and a second portion;

a second metallization layer formed on the substrate, the second metallization layer having a first portion and a second portion;

a dielectric layer between the first and second metallization layers;

a first electrically conducting via extending through the dielectric layer and in contact with the first portion of the first metallization layer and with the first portion of the second metallization layer;

a second electrically conducting via extending through the dielectric layer and in contact with the first portion of the second metallization layer and with the second portion of the first metallization layer; and

a third electrically conducting via extending through the dielectric layer and in contact with the second portion of the first metallization layer and with the second portion of the second metallization layer, wherein the first and second metallization layer are not configured to be in electrical communication with an interconnect structure on the substrate.

2. The interconnect test structure of claim 1 wherein:

the first portion of the first metallization layer includes a force node and a sense node;

the second portion of the first metallization layer includes a force node and a sense node;

the first portion of the second metallization layer includes a force node and a sense node; and

the second portion of the second metallization layer having a force node and a sense node.

3. The interconnect test structure of claim 2 wherein the force and sense nodes of the first and second metallization layers extend to a scribe line.

4. The interconnect test structure of claim 1 wherein the first metallization layer underlies the second metallization layer.

5. The interconnect test structure of claim 1 wherein the first metallization layer overlies the second metallization layer.

6. The interconnect test structure of claim 1 wherein the first and second metallization layers form successive metallization layers of the interconnect structure.

7. The interconnect test structure of claim 1 wherein at least one of the first and second metallization layers comprises copper.

8. The interconnect test structure of claim 1 wherein one of the first, second, and third vias comprises tungsten..

9. The interconnect test structure of claim 1 wherein the first and second portions of the first metallization layer, and the first and second portions of the second metallization layer, have a length of about 200 μ

m or greater.

10. An electromigration test method comprising:

disposing a test structure on a substrate, the test structure comprising,

a first metallization layer having a first portion and a second portion, and

a second metallization layer having a first portion and a second portion,

a dielectric layer between the first and second metallization layers,

a first electrically conducting via extending through the dielectric layer and in contact with the first portion of the first metallization layer and with the first portion of the second metallization layer,

a second electrically conducting via extending through the dielectric layer and in contact with the first portion of the second metallization layer and with the second portion of the first metallization layer, and

a third electrically conducting via extending through the dielectric layer and in contact with the second portion of the first metallization layer and with the second portion of the second metallization layer,

applying a force voltage to one of the first and second portions of one of the first and second metallization layers; and

detecting a changed sense voltage over time at another of the one of the first and second portions of one of the first and second metallization layers, wherein the changed sense voltage reveals electromigration in at least one of the first and second metallization layers.

11. The electromigration test method of claim 10 further comprising:

applying a second force voltage to a different one of the first and second portions of the one of the first and second metallization layers, the different one of the first and second portions of the one of the first and second metallization layers intermediate between a location of application of the force voltage and a location of detection of the changed sense voltage; and

detecting a second changed source voltage to locate a position of the electromigration in the test structure.

12. The electromigration test method of claim 10 wherein the force voltage is applied to a force node exposed by a scribe line, and the sense voltage is detected on a sense node exposed by the scribe line.

13. The electromigration test method of claim 10 further comprising changing a temperature of the substrate one of prior to and during application of the force voltage.

14. A method of fabricating an interconnect test structure comprising:

patterning a lower metallization layer on a substrate to form a first portion and a second portion not in contact with other portions of the first metallization layer;

forming a dielectric layer over the first metallization layer;

forming a first electrically conducting via extending through the dielectric layer in contact with a first end of the first portion of the first metallization layer;

forming a second electrically conducting via extending through the dielectric layer in contact with a second end of the first portion of the first metallization layer;

forming a third electrically conducting via extending through the dielectric layer in contact with a first end of the second portion of the first metallization layer; and

patterning a second metallization layer on the dielectric layer such that a first portion of the second metallization layer is in contact with the first conducting via, a first end of a second portion of the second metallization layer is in contact with the second conducting via, and a second end of the second portion of the second metallization layer is in contact with the third conducting via.

15. The method of claim 14 wherein:

the first metallization layer is patterned by electroplating metal within a first recess formed in the substrate, and then chemical mechanical polishing to remove the metal outside of the recess; and

the second metallization layer is patterned by electroplating metal within a second recess formed in the dielectric layer, and then chemical mechanical polishing to remove the metal outside of the second recess.

16. The method of claim 15 wherein copper metal is electroplated within the first and second recesses.

17. The method of claim 15 wherein the first, second, and third vias are formed by etching the dielectric layer to form via holes, and then depositing tungsten metal within the via holes.

18. The method of claim 15 further comprising forming on a scribe line of the substrate, a force node and a sense node of the first portion of the first metallization layer, a force node and a sense node of the second portion of the first metallization layer, a force node and a sense node of the first portion of the second metallization layer, and a force node and a sense node of the second portion of the second metallization layer.