Silicon carbide semiconductor device

• US 20080128711A1
• Filed: 11/08/2007
• Published: 06/05/2008
• Est. Priority Date: 04/19/2005
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Sakakibara, Toshio, Okuno, Eiichi
• Granted Patent: US 7,763,893 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices

Abstract

A silicon carbide semiconductor device includes a semiconductor element disposed in a semiconductor substrate having a first conductive type silicon carbide layer and a silicon substrate. The device includes: a trench on the silicon carbide layer to reach the silicon substrate; and a conductive layer in the trench between the silicon carbide layer and the silicon substrate to connect to both of them. The semiconductor element is a vertical type semiconductor element so that current flows on both of a top surface portion and a backside surface portion of the semiconductor substrate. The current flows through the conductive layer.

Claims

1. A silicon carbide semiconductor device including a semiconductor element, wherein the semiconductor element is disposed in a semiconductor substrate having a first conductive type silicon carbide layer and a silicon substrate, and wherein the first conductive type silicon carbide layer is disposed on a principal surface of the silicon substrate, the device comprising:

a trench disposed on a surface of the silicon carbide layer to reach the silicon substrate; and

a conductive layer disposed in the trench at a boundary portion between the silicon carbide layer and the silicon substrate to connect to both of the silicon carbide layer and the silicon substrate, wherein

the semiconductor element is a vertical type semiconductor element so that current flows on both of a top surface portion and a backside surface portion of the semiconductor substrate, and

the current flows through the conductive layer.

2. The silicon carbide semiconductor device according to claim 1, further comprising:

a low resistance layer disposed at a boundary portion between the silicon carbide layer and the silicon substrate in such a manner that an impurity concentration of a first conductive type impurity in the low resistance layer is higher than that of the silicon carbide layer, wherein

the trench penetrates the low resistance layer and reaches the silicon substrate, and

the conductive layer is disposed in the trench to connect between the low resistance layer and the silicon substrate.

3. The silicon carbide semiconductor device according to claim 1, further comprising:

an insulation film disposed on a sidewall of the trench.

4. The silicon carbide semiconductor device according to claim 1, wherein

the semiconductor element is a bipolar transistor having a base region and an emitter region disposed in the silicon carbide layer,

the base region has a second conductive type, and

the emitter region has the first conductive type.

5. The silicon carbide semiconductor device according to claim 1, wherein

the semiconductor element is a PN diode provided by a second conductive type layer in the silicon carbide layer.

6. The silicon carbide semiconductor device according to claim 1, wherein

the semiconductor element is a Schottky barrier diode provided by a metallic layer on a surface of the silicon carbide layer, and

the metallic layer contacts the surface of the silicon carbide layer with Schottky contact.

7. The silicon carbide semiconductor device according to claim 1, wherein

the semiconductor element is a vertical type power MOSFET including:

a base region having a second conductive type, which is disposed on a surface portion of the silicon carbide layer;

a source region having the first conductive type, which is disposed on a surface portion of the base region;

a gate insulation film disposed on a channel region, which is provided by a portion of the surface of the base region, the portion sandwiched between the silicon carbide layer and the source region;

a gate electrode disposed on the gate insulation film;

an interlayer insulation film for covering the gate electrode, wherein a contact hole is disposed in the interlayer insulation film for connecting to both of the source region and the base region; and

a source electrode for electrically connecting to both of the source region and the base region through the contact hole in the interlayer insulation film.

8. The silicon carbide semiconductor device according to claim 7, wherein

the vertical type power MOSFET is a planar type vertical power MOSFET, in which the channel region is parallel to the principal surface of the silicon substrate.

9. The silicon carbide semiconductor device according to claim 7, wherein

the vertical type power MOSFET is a trench type vertical power MOSFET having a second trench,

the second trench is disposed on the surface of the silicon carbide layer,

the gate insulation film and the gate electrode are disposed on the sidewall of the second trench,

the source region and the base region contact the sidewall of the second trench, and

the channel region is disposed on the sidewall of the second trench.

10. The silicon carbide semiconductor device according to claim 1, wherein

a part of the conductive layer is made of titanium, the part contacting the silicon substrate, and

another part of the conductive layer is made of nickel, the other part contacting the silicon carbide layer.

11. A silicon carbide semiconductor device including a semiconductor element, wherein the semiconductor element is disposed in a semiconductor substrate having a first conductive type silicon carbide layer and a silicon substrate, and wherein the first conductive type silicon carbide layer is disposed on a principal surface of the silicon substrate, the device comprising:

a trench disposed on a backside surface of the silicon substrate to reach the silicon carbide layer; and

a backside electrode disposed in the trench at a boundary portion between the silicon carbide layer and the silicon substrate to connect to both of the silicon carbide layer and the silicon substrate, wherein

the semiconductor element is a vertical type semiconductor element so that current flows on both of a foreside surface portion and a backside surface portion of the semiconductor substrate, and

the current flows through the backside electrode.

12. The silicon carbide semiconductor device according to claim 11, further comprising:

a low resistance layer disposed at a boundary portion between the silicon carbide layer and the silicon substrate in such a manner that an impurity concentration of a first conductive type impurity in the low resistance layer is higher than that of the silicon carbide layer, wherein

the trench reaches the low resistance layer, and

the backside electrode is disposed in the trench to connect between the low resistance layer and the silicon substrate.

13. The silicon carbide semiconductor device according to claim 11, wherein

a part of the backside electrode is made of titanium, the part contacting the silicon substrate, and

another part of the backside electrode is made of nickel, the other part contacting the silicon carbide layer.

14. The silicon carbide semiconductor device according to claim 11, wherein

the semiconductor element is a bipolar transistor having a base region and an emitter region disposed in the silicon carbide layer,

the base region has a second conductive type, and

the emitter region has the first conductive type.

15. The silicon carbide semiconductor device according to claim 11, wherein

the semiconductor element is a PN diode provided by a second conductive type layer in the silicon carbide layer.

16. The silicon carbide semiconductor device according to claim 11, wherein

the semiconductor element is a Schottky barrier diode provided by a metallic layer on a surface of the silicon carbide layer, and

the metallic layer contacts the surface of the silicon carbide layer with Schottky contact.

17. The silicon carbide semiconductor device according to claim 11, wherein

the semiconductor element is a vertical type power MOSFET including:

a base region having a second conductive type, which is disposed on a surface portion of the silicon carbide layer;

a source region having the first conductive type, which is disposed on a surface portion of the base region;

a gate insulation film disposed on a channel region, which is provided by a portion of the surface of the base region, the portion sandwiched between the silicon carbide layer and the source region;

a gate electrode disposed on the gate insulation film;

an interlayer insulation film for covering the gate electrode, wherein a contact hole is disposed in the interlayer insulation film for connecting to both of the source region and the base region; and

a source electrode for electrically connecting to both of the source region and the base region through the contact hole in the interlayer insulation film.

18. The silicon carbide semiconductor device according to claim 17, wherein

the vertical type power MOSFET is a planar type vertical power MOSFET, in which the channel region is parallel to the principal surface of the silicon substrate.

19. The silicon carbide semiconductor device according to claim 17, wherein

the vertical type power MOSFET is a trench type vertical power MOSFET having a second trench,

the second trench is disposed on the surface of the silicon carbide layer,

the gate insulation film and the gate electrode are disposed on the sidewall of the second trench,

the source region and the base region contact the sidewall of the second trench, and

the channel region is disposed on the sidewall of the second trench.