Trench MOSFET with cell layout to improve ruggedness

• US 20080128829A1
• Filed: 12/04/2006
• Published: 06/05/2008
• Est. Priority Date: 12/04/2006
• Status: Active Grant

• Current Assignee: Force-Mos Technology Corporation (Force Mos Technology Co., Ltd.)
• Original Assignee: Force-Mos Technology Corporation (Force Mos Technology Co., Ltd.)
• Inventors: Hshieh, Fwu-Iuan
• Granted Patent: US 7,812,409 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trenched semiconductor power device that includes a trenched gate disposed in an extended continuous trench surrounding a plurality of transistor cells wherein the layout of the trenched gate surrounding the transistor cells as closed cells having truncated corners or rounded corners. In an exemplary embodiment, the closed cells further includes a contact metal to contact a source and a body regions wherein the contact metal the trenched gate surrounding the transistor cell have a uniform space between them. In another exemplary embodiment, the semiconductor power device further includes a contact dopant region disposed below the contact metal to enhance an electrical contact between the metal contact and the source region and the body region, and the contact dopant region having substantially circular shape to achieve a uniform space between the contact dopant region and the trenched gate surrounding the closed cells.

Claims

1. A trenched semiconductor power device comprising a trenched gate disposed in an extended continuous trench surrounding a plurality of transistor cells, wherein:

said trenched gate surrounding said transistor cells as closed cells with truncated corners.

2. The trenched semiconductor power device of claim 1 wherein:

said closed cells further includes a contact metal to contact a source and a body regions of said semiconductor power device wherein said contact metal surrounded by said trenched gate with substantially a uniform space between them.

3. The trenched semiconductor power device of claim 2 further comprising:

a doped contact region disposed below said contact metal to enhance an electrical contact between the metal contact and the source region and the body region, and the doped contact region having substantially a uniform space between the contact dopant region and the trenched gate surrounding the closed cells.

4. The trenched semiconductor power device of claim 1 further comprising:

an insulation layer covering said power device having a source/body contact opened through said insulation and extended into an epitaxial layer in said semiconductor substrate for disposing a metal contact therein to contact a source region and a body region of said semiconductor power device wherein said contact opening disposed substantially at a center of an area surrounded by said trenched gate whereby there is substantially a uniform space between them.

5. The trenched semiconductor power device of claim 4 further comprising:

a contact resistance reduction layer composed of a low resistance metal for covering an interface area between said source region and said body region and said contact metal for reducing a contact resistance to said source region and said body region.

6. The trenched semiconductor power device of claim 5 wherein:

said contact resistance reduction layer composed of or Ti/TiN as said low resistance metal.

7. The trenched semiconductor power device of claim 4 further comprising:

a contact resistance reduction doped region comprising a region of high concentration dopant ions disposed below said contact opening for reducing a resistance of said contact metal to body region of said semiconductor power device.

(N+ is not disposed below contact for 2D contact structure)

8. The trenched semiconductor power device of claim 4 further comprising:

an insulation layer covering said power device having a source/body contact opened through said insulation layer and extended into said source and body regions for disposing a metal contact plug therein to contact a source region and a body region of said semiconductor power device wherein said source/body contact surrounded by said trenched gate having a substantially uniform space between them.

9. The trenched semiconductor power device of claim 8 wherein:

said contact metal plug disposed in said source/body contact trench further comprising a Ti/TiN/W metal plug.

10. The trenched semiconductor power device of claim 8 wherein:

said contact metal plug disposed in said source/body contact trench further comprising a Ti/TiN/Al alloy plug.

11. The trenched semiconductor power device of claim 8 further comprising:

a contact resistance reduction doped region disposed in said substrate comprising a region of high concentration dopant ions in contact with said source/body contact for reducing a resistance of said contact metal to said source region and body region of said semiconductor power device.

12. The trenched semiconductor power device of claim 1 further comprising:

said closed cells further includes a source/body contact metal to contact a source and a body regions of said semiconductor power device wherein said contact metal surrounded by said trenched gate with a ratio of a longest distance and a shortest distance between said source/body contact and the trenched gate is less than 1.414.

13. A trenched semiconductor power device comprising a trenched gate disposed in an extended continuous trench surrounding a plurality of transistor cells, wherein:

said trenched gate surrounding said transistor cells as closed cells with rounded corners.

14. A method for fabricating a trenched semiconductor power device comprising steps of forming a trenched gate as an extended continuous trench surrounding a plurality of transistor cells further comprising:

doping a source/body metal contact region in an area surrounded by said trenched gate at a location and shape such that there is substantially a uniform space between the doped metal contact region and the surrounding trenched gate.

15. The method of claim 14 further comprising:

doping the metal contact region having substantially a circular shape such that there is a substantially a uniform space between the doped metal contact region and the surrounding trenched gate.

16. The method of claim 14 further comprising:

opening said trenches with truncated corners surround the doped contact region whereby there is a uniform space between the doped contact region and the surrounding trenched gate.

17. The method of claim 14 further comprising:

opening said trenches with rounded corners surround the doped contact region whereby there is a uniform space between the doped contact region and the surrounding trenched gate.

18. The method of claim 14 further comprising:

forming a source/body contact metal to contact a source and a body regions of said semiconductor power device wherein said contact metal surrounded by said trenched gate with a ratio of a longest distance and a shortest distance between said source/body contact and the trenched gate is less than 1.414.