INTEGRATED THERMAL SYSTEMS

• US 20080128898A1
• Filed: 10/31/2007
• Published: 06/05/2008
• Est. Priority Date: 09/16/2005
• Status: Active Grant

• Current Assignee: University of Cincinnati
• Original Assignee: Progressive Cooling Solutions Incorporated
• Inventors: Shuja, Ahmed, Medis, Praveen, Parimi, Srinivas, Henderson, H. Thurman, Gerner, Frank M.
• Granted Patent: US 7,692,926 B2
• Time in Patent Office: Days
• US Class Current: 257/713
• CPC Class Codes: F28D 15/043 forming loops, e.g. capillary pumped loops
• CPC Class Codes: H01L 23/427 Cooling by change of state, e.g. use of heat pipes by liquefied gas H01L23/445
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: Y10S 165/218 Condensor adapted to cover opening at top of vapor generator
• CPC Class Codes: Y10T 29/49396 Condenser, evaporator or vaporizer making

Abstract

The present invention is a MEMS-based two-phase LHP (loop heat pipe) and CPL (capillary pumped loop) using semiconductor grade silicon and microlithographic/anisotropic etching techniques to achieve a planar configuration. The principal working material is silicon (and compatible borosilicate glass where necessary), particularly compatible with the cooling needs for electronic and computer chips and package cooling. The microloop heat pipes (μLHP™) utilize cutting edge microfabrication techniques. The device has no pump or moving parts, and is capable of moving heat at high power densities, using revolutionary coherent porous silicon (CPS) wicks. The CPS wicks minimize packaging thermal mismatch stress and improves strength-to-weight ratio. Also burst-through pressures can be controlled as the diameter of the coherent pores can be controlled on a sub-micron scale. The two phase planar operation provides extremely low specific thermal resistance (20-60 w/cm²). The operation is dependent upon a unique micropatterened CPS wick which contains up to millions per square centimeter of stacked uniform micro-through-capillaries in semiconductor-grade silicon, which serve as the capillary “engine,” as opposed to the stochastic distribution of pores in the typical heat pipe wick. As with all heat pipes, cooling occurs by virtue of the extraction of heat by the latent heat of phase change of the operating fluid into vapor.

In the cooling of a laptop computer processor the device could be attached to the processor during laptop assembly. Consistent with efforts to miniaturize electronics components, the current invention can be directly integrated with a unpackaged chip. For applications requiring larger cooling surface areas, the planar evaporators can be spread out in a matrix and integrally connected through properly sized manifold systems.

Claims

1. An integrated thermal bus system, the system comprising:

a plurality of heat sources;

one or more of a plurality of evaporators thermally coupled to one or more of the plurality of heat sources;

wherein an evaporator of the plurality of evaporators comprises semiconductor-based material, the semiconductor-based material comprising;

a first porous portion;

a second portion having a contact surface suitable for thermal coupling to the one or more of the plurality of heat sources;

at least one liquid inlet; and

at least one vapor outlet;

at least one heat transfer center;

wherein a heat transfer center of the at least one heat transfer center includes a vapor inlet and a liquid outlet;

a vapor bus system that couples the at least one vapor outlet to the vapor inlet of the at least one heat transfer center; and

a liquid bus system that couples the liquid outlet to the at least one liquid inlet of the one or more of the plurality of evaporators.

2. The system of claim 1, wherein the plurality of heat sources includes components of a computing system.

3. The system of claim 2, wherein the plurality of heat sources comprises at least one microprocessor.

4. The system of claim 1, wherein a heat transfer center of the at least one heat transfer center is a condenser.

5. The system of claim 4, wherein the condenser comprises substantially of, one or more of, copper-based substances, aluminum-based substances, and silver-based substances.

6. The system of claim 1, wherein, the first porous portion of the evaporator, comprises substantially of, coherent porous silicon.

7. An semiconductor substrate assembly, the assembly comprising:

a first region of the semiconductor substrate that is non-porous;

a second region of the semiconductor substrate that is porous; and

wherein, the first region of the semiconductor substrate is formed with integrated circuitry.

8. The assembly of claim 7, wherein a first surface of the second region of the semiconductor substrate is coupled to a condenser.

9. The assembly of claim 7, wherein the first surface of the second region of the semiconductor substrate is operatively configured to facilitate fluid evaporation.

10. The assembly of claim 7, wherein a second surface of the second region of the semiconductor substrate is couple-able to a liquid supply.

11. The assembly of claim 7, wherein, the second region of the semiconductor substrate comprises substantially of, coherent porous silicon.

12. The assembly of claim 7, wherein the semiconductor substrate is substantially comprised of, crystalline silicon.

13. The assembly of claim 12, wherein the crystalline silicon is in the [100] direction.

14. The assembly of claim 13, wherein the crystalline silicon is CMOS-grade n-type silicon.

15. The assembly of claim 7, wherein the second region of the semiconductor substrate comprises pores of a substantially high length to diameter aspect ratio.

16. The assembly of claim 15, wherein the second region of the semiconductor substrate comprises pores of a length to diameter aspect ratio of 60-200.