Configurable Integrated Circuit with Built-in Turns

• US 20080129333A1
• Filed: 11/26/2007
• Published: 06/05/2008
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Andre Rohe, Steve Teig
• Inventors: Teig, Steven, Rohe, Andre
• Granted Patent: US 7,737,722 B2
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

Some embodiments of the invention provide configurable integrated circuits (“IC'"'"'s”) with configurable node arrays. In some embodiments, the configurable node array includes numerous (e.g., 50, 100, etc.) configurable nodes arranged in several rows and columns. This array also includes several direct offset connections, where each particular direct offset connection connects two nodes that are neither in the same column nor in the same row in the array. In some embodiments, at least some direct offset connections connect pairs of nodes that are separated in the array by more than one row and at least one column, or by more than one column and at least one row. Some embodiments establish a direct connection by (1) a set of wire segments that traverse through a set of the IC'"'"'s wiring layers, and (2) a set of vias when two or more wiring layers are involved. In some embodiments, some of the direct connections have intervening circuits (e.g., buffer circuits), while other direct connections do not have any intervening circuits. Also, in some embodiments, the nodes in the configurable array are all similar (e.g., have the same set of circuit elements and same internal wiring between the circuit elements).

Claims

1. An integrated circuit (“

IC”

) comprising;

at least fifty configurable nodes arranged in an array having a plurality of rows and a plurality of columns; and

a plurality of sets of wire segments connecting a plurality of the configurable nodes;

wherein at least one set of wire segments connects two offset configurable nodes in the array without using intervening interconnect circuits, wherein two configurable nodes are offset when they are not in the same row or column in the array and are at least three rows or at least three columns apart.

2. The integrated circuit of claim 1, wherein a plurality of the wire segment sets connect several sets of offset nodes.

3. The integrated circuit of claim 2, wherein each of a plurality of the wire segment sets connects two nodes that are separated in the array by at least three rows and at least one column, or at least three columns and at least one row.

4. The integrated circuit of claim 3, wherein the wire segment sets that connect the pairs of nodes that are separated in the array by at least two rows and one column, or at least two columns and one row, are arranged in a repetitive architecture across the node array.

5. The integrated circuit of claim 2, wherein the wire segment sets are symmetrically arranged across the node array.

6. The integrated circuit of claim 2, wherein the wire segment sets are grouped into a plurality of groups of connections, wherein at least a first group of connections are symmetrically arranged on the node array with respect to a second group of connections.

7. The integrated circuit of claim 2, wherein the wire segment sets are arranged across the node array in a nested architecture.

8. The integrated circuit of claim 2, wherein the wire segment sets are asymmetrically arranged across the node array.

9. The integrated circuit of claim 2, wherein a plurality of wire segment sets include intervening buffer circuits.

10. The integrated circuit of claim 1, wherein the set of wire segments includes two different segments that are on two different wiring layers of the IC.

11. The integrated circuit of claim 1, wherein the set of wire segments includes a set of vias that connect the wire segments.

12. The integrated circuit of claim 1, wherein wire segments in the set of wire segments are only Manhattan directions except for jogs.

13. The integrated circuit of claim 1, wherein wire segments in the set of wire segments are only in non-Manhattan directions except for jogs.

14. The integrated circuit of claim 1, wherein wire segments in the set of wire segments are in at least one Manhattan direction and at least one non-Manhattan direction.

15. The integrated circuit of claim 1, wherein the nodes are configurable interconnect circuits.

16. The integrated circuit of claim 15, wherein the nodes are switchboxes.

17. (canceled)

18. An integrated circuit (“

IC”

) comprising;

a plurality of configurable interconnect circuits arranged in an array having a plurality of rows and a plurality of columns; and

a plurality of sets of wire segments connecting a plurality of the configurable interconnect circuits;

wherein at least one set of wire segments connects two offset configurable interconnect circuits in the array that are separated in the array by at least three rows and at least one column, or at least three columns and at least one row without using any interconnect circuits.

19. The IC of claim 18, wherein the wire segments are symmetrically arranged across the IC.

20. An integrated circuit (“

IC”

) comprising;

a plurality of configurable logic circuits arranged in an array having a plurality of rows and a plurality of columns; and

a plurality of sets of wire segments connecting a plurality of the configurable logic circuits;

wherein at least one set of wire segments connects two offset configurable logic circuits in the array that are separated in the array by at least two rows and one column, or at least two columns and at least one row without using any intervening interconnect circuits.