Method and apparatus for performing shifting in an integrated circuit

• US 20080129337A1
• Filed: 10/31/2007
• Published: 06/05/2008
• Est. Priority Date: 03/15/2005
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Brad Hutchings, Herman Schmit, Jason Redgrave, Steve Teig
• Inventors: Teig, Steven, Redgrave, Jason, Hutchings, Brad, Schmit, Herman
• Granted Patent: US 7,528,627 B2
• Time in Patent Office: Days
• US Class Current: 326/62
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit can interchangeably perform as either a logic circuit or an interconnect circuit in the configurable IC.

Claims

1-51. -51. (canceled)

52. For an integrated circuit (IC), a shifter circuit for receiving an n-bit data set and outputting the n-bit data set shifted an amount of zero through m bits, the shifter comprising:

a plurality of multiplexers comprising input, output, and select terminal sets, each multiplexer for;

a) receiving the n-bit data set;

b) receiving a set of control signals on its select terminal set, wherein the set of control signals comprises at least one user signal generated within the IC; and

c) outputting a portion of the n-bit data set based on the set of control signals.

53. The shifter circuit of claim 52, wherein the user signal is an output of a configurable logic circuit of the IC.

54. The shifter circuit of claim 52, wherein m is a number that is less than n.

55. The shifter circuit of claim 52, wherein the n-bit data set is an output of at least one configurable logic circuit of the IC, said configurable logic circuit for configurably performing a plurality of logic operations.

56. The shifter circuit of claim 55, wherein the n-bit data set is provided to the shifter circuit by a configurable interconnect circuit of the IC, said configurable interconnect circuit for configurably routing signals between configurable logic circuits.

57. An integrated circuit (IC) comprising:

a) a set of configurable logic circuits for configurably performing a plurality of logic operations; and

b) a shifter formed by a plurality of multiplexers comprising input, output, and select terminal sets, wherein the shifter is for receiving n bits of data and outputting the n bits of data shifted by m bits, said outputting controlled by a set of outputs of at least one configurable logic circuit that is supplied to select terminals of the multiplexers of the shifter.

58. The IC of claim 57, wherein m is a number less than n.

59. A method for performing a shift operation on an n-bit data set in an integrated circuit (IC), the IC comprising (1) a shifter comprising a set of multiplexers comprising input, output, and select terminal sets and (2) a set of configurable circuits for configurably performing a set of logic operations and outputting a set of user signals, the method comprising:

receiving the n-bit data set at the shifter;

receiving a set of user signals at select lines of at least one multiplexer of the shifter; and

from the at least one multiplexer, outputting a portion of the n-bit data set, said portion allowing the shifter to shift the n-bit data set by an amount of m bits.

60. The method of claim 59, wherein m is a number less than n.

62. The shifter circuit of claim 60, wherein said shifter circuit comprises exactly n multiplexers that each receive n bits of input and provide one bit of output.

63. The shifter circuit of claim 60, wherein each multiplexer of the shifter circuit receives the n-bit data set.

64. The shifter circuit of claim 60, wherein a first multiplexer of the shifter circuit receives a permutation of the n-bit data set that is different from a permutation of the n-bit data set received by a second multiplexer of the shifter.

65. The shifter circuit of claim 64, wherein each multiplexer of the shifter receives a different permutation of the set of input data.

66. The shifter circuit of claim 60, wherein the shifter circuit performs a right shift on the n-bit data set.

67. The shifter circuit of claim 60, wherein the shifter circuit performs a left shift on the n-bit data set.

61. For an integrated circuit (IC) a shifter circuit comprising:

a plurality of multiplexers comprising input, output, and select terminal sets, wherein the shifter is for;

a) receiving an n-bit data set;

b) receiving a set of control signals at a select terminal set of at least one multiplexer of the shifter, wherein the set of control signals comprises at least one user signal generated within the IC; and

c) outputting the n-bit data set shifted by an amount of m bits.