VOLTAGE SUPPLIER OF SEMICONDUCTOR MEMORY DEVICE

• US 20080129373A1
• Filed: 02/06/2008
• Published: 06/05/2008
• Est. Priority Date: 05/06/2004
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Jae-Jin, LEE, Kang-Seol
• Granted Patent: US 7,514,986 B2
• Time in Patent Office: Days
• US Class Current: 327/536
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence

Abstract

The present invention provides voltage supplier for supplying an internal voltage with optimized drivability required for internal operation. The voltage supplier of a semiconductor memory device includes: an internal voltage detection means for detecting a voltage level of an internal voltage; a clock oscillation means for outputting a charge pumping clock signal; an internal voltage control means for controlling the clock oscillation means to be performed selectively in accordance with a data access mode or a non-data access mode; and a charge pumping means for outputting the internal voltage required for internal operation by pumping charges in response to the charge pumping clock signal.

Claims

1. A voltage supplier of a semiconductor memory device comprising:

an internal voltage detection means for detecting a voltage level of an internal voltage;

a clock oscillation means for outputting a charge pumping clock signal;

an internal voltage control means for controlling the clock oscillation means to be performed selectively in accordance with a data access mode or a non-data access mode; and

a charge pumping means for outputting the internal voltage required for internal operation by pumping charges in response to the charge pumping clock signal.

2. The voltage supplier as recited in claim 1, wherein the clock oscillation means outputs the charge pumping clock signal by receiving a first clock signal or a second clock signal, wherein the first clock signal is outputted as the charge pumping signal in the non-data access mode and the second clock signal is outputted as the charge pumping signal in the data access mode.

4. The voltage supplier as recited in claim 2, wherein the first clock signal is oscillated in the clock oscillation means in response to the voltage level of the internal voltage which is detected at the internal voltage detection means.

5. The voltage supplier as recited in claim 1, wherein the data access mode is an operational period selected from a group consisting of an active command, a read/write command and an auto refresh command.

6. The voltage supplier as recited in claim 1, wherein the non-data access mode is a period of a self refresh mode or a standby mode.

7. The voltage supplier as recited in claim 1, wherein the internal voltage control means includes:

a frequency divider for dividing an external clock by a predetermined period corresponding to current consumed during the data access;

a control signal generator for outputting a control signal in response to an active command; and

a clock signal output unit for outputting the clock signal divided by the frequency divider as the second clock signal, which is activated by the control signal.

8. The voltage supplier as recited in claim 7, wherein the internal voltage control means further includes a transfer gate for transferring the external clock signal to the clock signal output unit, which is selectively enabled with the frequency divider.

9. The voltage supplier as recited in claim 1, wherein the clock oscillation means includes:

a signal transferring unit for transferring the detection signal, which is activated in response to the control signal;

a clock oscillation unit for oscillating and outputting the first clock signal in response to the detection signal; and

a signal combination unit for outputting the oscillated first clock signal or the second clock signal as the charge pumping signal.

10. The voltage supplier as recited in claim 9, wherein the clock oscillation unit is configured with a ring oscillator.

11. The voltage supplier as recited in claim 9, wherein the signal transferring unit includes:

a first inverter for inverting the control signal; and

a first NAND gate for performing a NAND operation to the output of the first inverter and the detection signal.

12. The voltage supplier as recited in claim 9, wherein the clock oscillation unit includes:

a first NOR gate where the output of the first NAND gate is inputted to one end thereof; and

a plurality of inverters for inverting the output of the first NOR gate and outputting the inverted signal to the other end of the first NOR gate, in which the plurality of inverters are connected in series to form a closed loop circuit with the first NOR gate.

13. The voltage supplier as recited in claim 12, wherein the clock oscillation unit further includes a plurality of capacitors for adjusting an output load of each inverter in the closed loop circuit.

14. The voltage supplier as recited in claim 9, wherein the signal combination unit includes:

a second NOR gate for performing a NOR operation to the output of the first NOR gate and the second clock signal;

a second inverter for inverting the second clock signal;

a second NAND gate for performing a NAND operation to the output of the second inverter and the output of an inverter among the plurality of inverters in the clock oscillation unit; and

a first buffer for buffering the output of the second NAND gate; and

a second buffer for buffering the output of the second NOR gate.

15. The voltage supplier as recited in claim 1, further comprising a voltage clamping means for preventing the internal voltage outputted from the charge pumping means from extremely being increased or decreased.

3. The voltage supplier as recited in claim 3, wherein the internal voltage control means supplies the second clock signal to the clock oscillation means having a predetermined period corresponding to current consumed during the data access mode, in which the oscillation operation of the clock oscillation means is not performed while the second clock signal is supplied thereto.