Display panel and display apparatus having the same

• US 20080129717A1
• Filed: 12/04/2007
• Published: 06/05/2008
• Est. Priority Date: 12/04/2006
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeon, Sang-jin, Baek, Seung-Soo, Lee, Min-Cheol, Lee, Yong-Soon, Park, Hee-Bum
• Granted Patent: US 8,558,776 B2
• Time in Patent Office: Days
• US Class Current: 345/204
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3677 suitable for active matrices only

Abstract

In a display panel and a display apparatus having the display panel, the display panel includes array and opposite substrates. The array substrate includes display and peripheral areas. Gate and source lines are formed in the display area. A gate driving part and first and second clock lines are formed in the peripheral area. The gate driving part outputs gate signals to the gate line. The first and second clock lines respectively transmit first and second clock signals to the gate driving part. The opposite substrate is combined with the array substrate and includes a common electrode layer. The common electrode layer has an opening portion patterned to expose the first and second clock lines. The exposed portions of the first and second clock lines have substantially the same area. Thus, delays of the gate signals may be minimized and distortion of the gate signals may be prevented.

Claims

1. A display panel comprising:

an array substrate including a display area and a peripheral area, gate lines and source lines being formed in the display area, a gate driving part and first and second clock lines being formed in the peripheral area, the gate driving part outputting gate signals to the gate line, and the first and second clock lines respectively transmitting first and second clock signals to the gate driving part; and

an opposite substrate combined with the array substrate and including a common electrode layer, the common electrode layer having an opening portion patterned to expose the first and second clock lines, and the exposed portions of the first and second clock lines having substantially a same area.

2. The display panel of claim 1, wherein the peripheral area comprises a first peripheral area and a second peripheral area and wherein the gate driving part comprises:

a first gate driving part formed in the first peripheral area that is adjacent to a first end portion of the gate lines, to output the gate signals to the gate lines; and

a second gate driving part formed in the second peripheral area that is adjacent to a second end portion of the gate lines, to output the gate signals to the gate lines.

3. The display panel of claim 1, wherein the peripheral area comprises a first peripheral area and a second peripheral area, the gate lines include even numbered gate lines and odd numbered gate lines, and wherein the gate driving part comprises:

a first gate driving part formed in the first peripheral area that is adjacent to a first end portion of the gate lines, to output the gate signals to the odd numbered gate lines; and

a second gate driving part formed in the second peripheral area that is adjacent to a second end portion of the gate lines, to output gate signals to the even numbered gate lines.

4. The display panel of claim 1, further comprising a sealant formed around the array substrate to combine the array substrate with the opposite substrate,

wherein areas of the first and second clock lines that are covered by the sealant are substantially the same.

5. The display panel of claim 1, further comprising first and second pad electrodes respectively formed at end portions of the first and second clock lines on the array substrate,

wherein areas of the first and second pad electrodes are substantially the same.

6. A display apparatus comprising:

a display panel including a display area and a peripheral area, gate and source lines being formed in the display area, a gate driving part and first and second clock lines being formed in the peripheral area, the gate driving part outputting gate signals to the gate line, the first and second clock lines respectively transmitting first and second clock signals to the gate driving part, and the first and second clock signals having substantially same time constant;

a source tape carrier package (TCP) on which a source driving chip outputting a data signal to the source lines is mounted, including dummy terminals electrically connected to the first and second clock lines to receive the first and second clock signals; and

a source printed circuit board (PCB) electrically connected to the display panel through the source TCP.

7. The display apparatus of claim 6, wherein pixels having different colors are connected to the source lines, and a relatively longer side of each pixel is aligned in an extended direction of the gate line and a relatively shorter side of each pixel is aligned in an extended direction of the source line.

8. The display apparatus of claim 6, wherein the peripheral area comprises a first peripheral area and a second peripheral area and wherein the gate driving part comprises:

a first gate driving part formed in the first peripheral area that is adjacent to a first end portion of the gate line, to output the gate signals to the gate line; and

a second gate driving part formed in the second peripheral area that is adjacent to a second end portion of the gate line, to output the gate signals to the gate line.

9. The display apparatus of claim 6, wherein the display panel comprises an array substrate having the first and second clock lines formed thereon, and an opposite substrate having a common electrode layer formed thereon and facing the array substrate.

10. The display apparatus of claim 9, wherein the common electrode layer comprises an opening portion patterned corresponding to an area in which the first and second clock lines are formed, and areas of the first and second clock lines exposed through the opening portion are substantially the same.

11. The display apparatus of claim 9, further comprising a sealant formed around the array substrate to combine the array substrate with the opposite substrate,

wherein areas of the first and second clock lines that are covered by the sealant are substantially the same.

12. The display apparatus of claim 6, wherein end portions of the first and second clock lines respectively further comprise first and second pad electrodes on which the dummy terminals are mounted.

13. The display apparatus of claim 12, wherein areas of the first and second pad electrodes are substantially the same.

14. The display apparatus of claim 12, wherein the numbers of the dummy terminals assigned to each of the first and second pad electrodes are substantially the same.

15. The display apparatus of claim 6, further comprising a main PCB electrically connected to the source PCB through a flexible PCB (FPCB), and having a main driving circuit that is mounted on the main PCB and outputs the first and second clock signals.

16. The display apparatus of claim 15, wherein the main PCB comprises first and second resistance elements formed on the main PCB, which are electrically connected to first and second output terminals of the main driving circuit outputting the first and second clock signals, respectively, and

the first and second resistance elements compensate for a time constant difference between the first and second clock signals.

17. The display apparatus of claim 16, wherein the first and second resistance elements are variable resistors.