METHODS AND SYSTEMS FOR UPDATING A BUFFER
First Claim
1. A method for updating a buffer having a plurality of lines associated with a display to prevent image tearing, comprising:
- (a) determining a read line position in the buffer, the read line position, indicating a line currently being read from the buffer, wherein the buffer is written to by a first processor and is read by a second processor;
(b) partitioning the buffer into at least a first section that is safe to update and a second section that must not be updated based on the read line position; and
(c) writing data at a line of the first section to update the buffer, wherein the line fallows the second section based on the read line position.
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Accused Products
Abstract
The present invention relates to methods and systems for updating a buffer. In one aspect, the present invention provides a method for updating a buffer, which includes strategically writing to the buffer to enable concurrent read and write to the buffer. The method eliminates the need for double buffering, thereby resulting in implementation cost sad space saving'"'"'s compared to conventional buffering approaches. The method also prevents image tearing when, used to update a frame buffer associated with a display, but is not limited to such applications. In another aspect, the present: invention provides efficient mechanisms to enable buffer update across a communication link. In one example, the present invention provides a method for relaying timing information across a communication link.
131 Citations
24 Claims
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1. A method for updating a buffer having a plurality of lines associated with a display to prevent image tearing, comprising:
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(a) determining a read line position in the buffer, the read line position, indicating a line currently being read from the buffer, wherein the buffer is written to by a first processor and is read by a second processor; (b) partitioning the buffer into at least a first section that is safe to update and a second section that must not be updated based on the read line position; and (c) writing data at a line of the first section to update the buffer, wherein the line fallows the second section based on the read line position. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for conveying timing information across a communication link between a first processor and a second processor to prevent image tearing in a display, wherein the communication link is in hibernation mode, comprising:
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scheduling a time event at the first processor to convey the timing information to the second processor; initiating a link wakeup by the first processor at the occurrence of the time event; and detecting the link wakeup at the second, processor, and using the detected link wakeup timing to synchronize the first and second processors with respect to the conveyed timing information. - View Dependent Claims (10, 11, 12)
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13. A system for updating a buffer having a plurality of lines associated with a display to prevent image tearing, comprising:
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means for determining a read line position in the buffer, the read line position indicating a line currently being read, from the buffer, wherein the buffer is written to by a first processor and is read by a second processor; means for partitioning the buffer into at least a first section that is safe to update and a second section that must not be updated based on the read line position; and means for writing data at a line of the first section to update the buffer, wherein the line follows the second section based on the read line position. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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21. A system for conveying timing information across a communication link between a first processor and a second processor to prevent image tearing in a display, wherein the communication link is in hibernation mode, comprising:
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means for scheduling a time event at the first processor to convey the timing information to the second processor; means for initiating a link wakeup by the first processor at the occurrence of the time event; and means for detecting the link wakeup at the second processor, and using the detected link wakeup timing to synchronize the first and second processors with respect to the conveyed timing information. - View Dependent Claims (22, 23, 24)
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Specification