Hybrid-Level Three-Dimensional Memory

• US 20080130342A1
• Filed: 04/18/2007
• Published: 06/05/2008
• Est. Priority Date: 12/01/2006
• Status: Abandoned Application

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: ZHANG, Guobiao
• Application Number:
  US11/736,767
• Publication Number:
  US 20080130342A1
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The present invention discloses a hybrid-level three-dimensional memory (HL-3DM). Some of its memory levels are separated, i.e. there is an inter-level dielectric between adjacent memory levels; while others are interleaved, i.e. adjacent memory levels share address-selection lines. The HL-3DM is particularly suitable for 3D-M with a large number of memory levels (m).

Claims

1. A hybrid-level three-dimensional memory (HL-3DM), comprising:

a substrate including transistors;

a first memory level above said substrate;

a second memory level above said first memory level, wherein said first and second memory levels share at least one address-selection line;

a third memory level adjacent to said first or second memory level, wherein said third memory level does not share address-selection line with either said first memory level or second memory level.

2. The HL-3DM according to claim 1, wherein the total number of memory levels in said 3D-M is no less than 4.

3. The HL-3DM according to claim 1, wherein all of said memory levels are mask-programmable or electrically-programmable.

4. The HL-3DM according to claim 1, wherein selected ones of said memory levels are mask-programmable and the other ones of said memory levels are electrically-programmable.

5. The HL-3DM according to claim 1, wherein at least one of said first, second and third memory levels comprises active devices.

6. The HL-3DM according to claim 5, wherein said active devices comprise transistors.

7. The HL-3DM according to claim 1, wherein at least one of said first, second and third memory levels comprises passive devices.

8. The HL-3DM according to claim 7, wherein said passive devices comprise diodes.

9. A hybrid-level three-dimensional memory (HL-3DM), comprising:

a substrate including transistors;

a first memory level above said substrate;

a second memory level above said first memory level, wherein said first and second memory levels share at least one address-selection line;

a third memory level above said second memory level, wherein said third memory level is separated from said second memory level by an inter-level dielectric.

10. The HL-3DM according to claim 9, wherein the number of memory levels in said 3D-M is no less than 4.

11. The HL-3DM according to claim 10, wherein all of said memory levels are mask-programmable or electrically-programmable.

12. The HL-3DM according to claim 10, wherein selected ones of said memory levels are mask-programmable and the other ones of said memory levels are electrically-programmable.

13. The HL-3DM according to claim 9, wherein at least one of said first, second and third memory levels comprises active devices.

14. The HL-3DM according to claim 9, wherein at least one of said first, second and third memory levels comprises passive devices.

15. A hybrid-level three-dimensional memory (HL-3DM), comprising:

a substrate including transistors;

a first memory level above said substrate;

a second memory level above said first memory level, wherein said first memory level is separated from second memory level by an inter-level dielectric;

a third memory level above said second memory level, wherein said second and third memory levels share at least one address-selection line.

16. The HL-3DM according to claim 15, wherein the number of memory levels in said 3D-M is no less than 4.

17. The HL-3DM according to claim 15, wherein all of said memory levels are mask-programmable or electrically-programmable.

18. The HL-3DM according to claim 15, wherein selected ones of said memory levels are mask-programmable and the other ones of said memory levels are electrically-programmable.

19. The HL-3DM according to claim 15, wherein at least one of said first, second and third memory levels comprises active devices.

20. The HL-3DM according to claim 15, wherein at least one of said first, second and third memory levels comprises passive devices.