Hybrid-Level Three-Dimensional Memory
First Claim
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1. A hybrid-level three-dimensional memory (HL-3DM), comprising:
- a substrate including transistors;
a first memory level above said substrate;
a second memory level above said first memory level, wherein said first and second memory levels share at least one address-selection line;
a third memory level adjacent to said first or second memory level, wherein said third memory level does not share address-selection line with either said first memory level or second memory level.
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Abstract
The present invention discloses a hybrid-level three-dimensional memory (HL-3DM). Some of its memory levels are separated, i.e. there is an inter-level dielectric between adjacent memory levels; while others are interleaved, i.e. adjacent memory levels share address-selection lines. The HL-3DM is particularly suitable for 3D-M with a large number of memory levels (m).
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Citations
20 Claims
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1. A hybrid-level three-dimensional memory (HL-3DM), comprising:
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a substrate including transistors; a first memory level above said substrate; a second memory level above said first memory level, wherein said first and second memory levels share at least one address-selection line; a third memory level adjacent to said first or second memory level, wherein said third memory level does not share address-selection line with either said first memory level or second memory level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A hybrid-level three-dimensional memory (HL-3DM), comprising:
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a substrate including transistors; a first memory level above said substrate; a second memory level above said first memory level, wherein said first and second memory levels share at least one address-selection line; a third memory level above said second memory level, wherein said third memory level is separated from said second memory level by an inter-level dielectric. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A hybrid-level three-dimensional memory (HL-3DM), comprising:
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a substrate including transistors; a first memory level above said substrate; a second memory level above said first memory level, wherein said first memory level is separated from second memory level by an inter-level dielectric; a third memory level above said second memory level, wherein said second and third memory levels share at least one address-selection line. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification