Byte-Erasable Nonvolatile Memory Devices

• US 20080130367A1
• Filed: 02/07/2008
• Published: 06/05/2008
• Est. Priority Date: 07/13/2005
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Chang-Hun, Hong, Eun-Mi, Kang, Sung-Taeg, Han, Jeong-Uk, Jeon, Hee-Seog, Jeon, Chang-Min, Seo, Bo-Young
• Application Number:
  US12/027,735
• Publication Number:
  US 20080130367A1
• Time in Patent Office: Days
• US Class Current: 365/185.13
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile memory device includes a semiconductor well region of first conductivity type on a semiconductor substrate and a common source diffusion region of second conductivity type extending in the semiconductor well region and forming a P-N rectifying junction therewith. A byte-erasable EEPROM memory array is provided in the semiconductor well region. This byte-erasable EEPROM memory array is configured to support independent erasure of first and second pluralities of EEPROM memory cells therein that are electrically connected to the common source diffusion region.

Claims

1. A memory device, comprising:

a semiconductor substrate including a first well of a first conductivity type and a second well of a second conductivity type, the second well being within the first well;

a memory cell array including a plurality of memory cells within the second well, the memory cell array including a first and a second group of byte number memory cells in a respective row of the memory cell array; and

a first and a second byte selection transistors in the first well and electrically coupled to first and second groups of byte number memory cells, respectively.

2. The memory device of claim 1, wherein the first byte selection transistor is located at one side of the second well and the second byte selection transistor is located at the second side of the second well, the second side being opposite to the first side.

3. The memory device of claim 1, wherein each of the memory cells comprises a first bit selection transistor, a memory cell transistor and a second bit transistor serially connected along a column direction;

wherein each row of the memory cell array first group of byte number memory cell transistors and second group of byte number memory cell transistors, control gates of the first group of byte number memory cell transistors being connected to form a first local control line, and control gates of the second group of byte number memory cell transistors being connected to form a second local control line; and

wherein the first local control line is connected to the first byte selection transistor, and the second local control line is connected to the second byte selection transistor.

4. The memory device of claim 3, further comprising:

a bit line electrically connected to the first bit selection transistors arranged in the column direction;

a common source line electrically connected to the second bit line selection transistors arranged in a row direction; and

a global control line electrically connected to byte selection transistors arranged in the row direction.

5. The memory device of claim 1, wherein each of the memory cells comprises a bit selection transistor and is serially connected along a column direction;

wherein each row of the memory cell array comprises a first group of byte number memory cell transistors and a second group of byte number memory cell transistors, control gates of the first group of byte number memory cell transistors being connected to form a first local control line, and control gates of the second group of byte number memory cell transistors being connected to form a second local control line; and

wherein the first local control line is connected to the first byte selection transistor, and the second local control line is connected to the second byte selection transistor.

6. The memory device of claim 5, further comprising:

a bit line electrically connected to memory cell transistors arranged in the column direction;

a common source line electrically connected to bit selection transistors arranged in the column direction; and

a global control line electrically connected to byte selection transistors arranged in the column direction.

7. The memory device of claim 1, wherein the first conductivity is n-type and the second conductivity is p-type.

8. A memory device, comprising:

a first well in a semiconductor substrate;

a second well within the first well;

a memory cell array including a plurality of memory cells arranged in a row and a column, each of the memory cells including a first bit selection transistor of a first conductivity type, a memory cell transistor of the first conductivity type and a second bit selection transistor of the first conductivity type; and

a plurality of byte selection transistors within the first well, each of the byte selection transistors being electrically connected to byte number memory cell transistors in a respective row of the memory cell array.

9. The memory device of claim 8, wherein a control gate of byte number memory cell transistors in a respective row are connected so as to form a first local control line and a second local control line in the respective row, the first local control line and the second local control line are electrically connected to different byte selection transistors, respectively.

10. The memory device of claim 9, further comprising:

a plurality of global control lines, each of the plurality of global control lines being electrically connected to byte selection transistors arranged in a row direction;

a plurality of bit lines, each of the bit lines being electrically connected to first bit selection transistors arranged in a row direction; and

a plurality of common source lines, each of the common source lines being electrically connected to second bit selection transistors arranged in the row direction.

11. The memory device of claim 9, wherein the memory cells are programmed by F-N tunneling when a negative voltage is applied to a selected second well, a positive voltage is applied to a selected global control line, a voltage lower than the positive voltage applied to the selected global control line is applied to a non-selected global control line or the non-selected global line is floated, a selected byte selection transistor is turned on and a non-selected byte selection transistor is turned off, the first bit selection transistor is turned on such that the same voltage as the negative voltage applied to the selected second well is applied to a selected bit line, and a voltage higher than that applied to the negative voltage applied to the selected second well is applied to a non-selected bit line.

12. The memory device of claim 9, wherein the memory cells are erased by F-N tunneling when a positive voltage is applied to a selected second well, a negative voltage is applied to a selected global control line, a voltage higher than the negative voltage applied to the selected global control line is applied to a non-selected global control line or the non-selected global line is floated, a selected byte selection transistor is on state and a non-selected byte selection transistor is turned off, and the first bit selection transistor and the second byte transistor are turned off.

13. The memory device of claim 9, wherein the first well is n-type and the second well is p-type.

14. A memory device, comprising:

a first well of a first conductivity type in a substrate;

a plurality of spaced apart second wells of a second conductivity type within the first well, each of the plurality of spaced apart second wells including a memory array including a plurality of memory cells arranged in a row and a column; and

a first and a second byte selection transistors within the first well and both sides of each of the second wells, the first byte selection transistor and the second byte selection transistors being electrically coupled to first and second byte number memory cells of the same row of respective second well, respectively.

15. The memory device of claim 14, wherein the first conductivity is n-type and the second conductivity is p-type.

16. The memory device of claim 14, wherein each of the memory cells comprises a first bit selection transistor, a memory cell transistor and a second bit transistor serially connected along a column direction;

wherein each row of the memory cell array comprises a first group of byte number memory cell transistors and a second group of byte number memory cell transistors, control gates of the first group of byte number memory cell transistors being connected to form a first local control line, and control gates of the second group of byte number memory cell transistors being connected to form a second local control line; and

wherein the first local control line is connected to the first byte selection transistor, and the second local control line is connected to the second byte selection transistor.

17. The memory device of claim 16, wherein a distance between the first and the second local control line is narrower than a distance between adjacent second walls.

18. The memory device of claim 16, wherein a line width of the first and the second bit selection transistors is wider than a line width of the memory cell transistor.

19. A memory device, comprising:

a first well of a first conductivity in a substrate;

a plurality of spaced apart second wells of a second conductivity type within the first well;

a plurality of memory cells arranged in a row and a column, each of the plurality of memory cells including a memory cell transistor and a bit selection transistor serially connected in a column direction, a line width of the memory cell transistor and a line width of the bit section transistor are different from each other; and

a byte selection transistor within the first well and electrically coupled to byte number memory cell transistors in a respective row.

20. The memory device of claim 19, wherein a line width of the memory cell transistor is narrower than a line width of the bit selection transistor.

21. The memory device of claim 19, wherein gates of the bit selection transistors arranged in a row direction are connected to form a bit selection line, control gate of the byte number memory cell transistors arranged in the row direction are connected to form a local control line, and adjacent bit selection lines in the row are connected through a local interconnection, and wherein a contact between the local interconnection and the bit selection line is formed within the first well.