Permute Unit and Method to Operate a Permute Unit

• US 20080130871A1
• Filed: 10/16/2007
• Published: 06/05/2008
• Est. Priority Date: 10/17/2006
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Wendel, Dieter, Leenstra, Jens, Gemmeke, Tobias
• Granted Patent: US 8,312,069 B2
• Time in Patent Office: Days
• US Class Current: 380/28
• CPC Class Codes: G06F 13/4217 with synchronous protocol
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A permute unit is described comprising a permute logic and a crossbar working in cycles defined by clocking signals and generating one valid output vector per cycle by treating two parallel input vectors per cycle according to an adequate scheme, wherein the permute unit is double pumped by performing two inner cycles per outer cycle defined by the clocking signals, wherein in every first inner cycle first halves of both input vectors are treated and in every second inner cycle second halves of both input vectors are treated and wherein every second inner cycle a valid output vector is generated from the results of the treatments within the first and the second inner cycles. Furthermore a method is described to operate such a permute unit.

Claims

1. A permute unit comprising:

a permute logic and a crossbar working in cycles defined by clocking signals and generating one valid output vector (v_o) per cycle by treating two parallel input vectors (v_a, v_b) per cycle according to an adequate scheme, wherein the permute unit is double pumped by performing two inner cycles per outer cycle defined by the clocking signals, wherein in every first inner cycle first halves (v_a<

0;

63>

, v_b<

0;

63>

) of both input vectors (v_a, v_b) are treated and in every second inner cycle second halves (v_a<

64;

127>

, v_b<

64;

127>

) of both input vectors (v_a, v_b) are treated and wherein every second inner cycle a valid output vector (v_o) is generated from the results of the treatments within the first and the second inner cycles.

2. The permute unit according to claim 1, further comprising:

means for successively treating pairs of halves (v_a<

0;

63>

, v_b<

0;

63>

, v_a<

64;

127>

, v_b<

64;

127>

) of parallel input vectors (v_a, v_b) according to an adequate scheme, means for considering successively treated pairs of halves (v_a<

0;

63>

, v_b<

0;

63>

, v_a<

64;

127>

, v_b<

64;

127>

) of the input vectors (v_a, v_b) when applying the adequate scheme, and

means for generating a valid output vector (v_o) every second inner cycle.

3. The permute unit according to claim 2, wherein the means for successively treating pairs of halves (v_a<

0;

63>

, v_b<

0;

63>

, v_a<

64;

127>

, v_b<

64;

127>

) of parallel input vectors (v_a, v_b) according to an adequate scheme comprise at least a double pumped permute logic.

4. The permute unit according to claim 3, wherein the means for considering successively treated pairs of halves (v_a<

0;

63>

, v_b<

0;

63>

, v_a<

64;

127>

, v_b<

64;

127>

) of the input vectors (v_a, v_b) when applying the adequate scheme comprise a feedback-loop providing information about the treatment in the first inner cycle to the treatment in the second inner cycle.

5. The permute unit according 4, wherein the means for generating a valid output vector (v_o) every second inner cycle comprise a feedback network that delays the result of the treatment of every first inner cycle by one inner cycle.

6. The permute unit according to claim 5, further comprising:

means for dividing pairs of parallel received input vectors into successive pairs of first and second halves.

7. The permute unit according to claim 6, wherein the adequate scheme according to which the pairs of first and second halves of the input vectors are treated is affected by an operand vector (v_c) that is provided to the permute unit in parallel to the parallel input vectors (v_a, v_b).

8. A method to operate a double pumped permute unit comprising the steps of

double pumping a permute unit by performing two inner cycles per outer cycle given by a clock signal,

treating a first pair of first halves (v_a<

0;

63>

, v_b<

0;

63>

) of two parallel input vectors (v_a, v_b) according to an adequate scheme in a first inner cycle,

treating a second pair of second halves (v_a<

64;

127>

, v_b<

64;

127>

) of two parallel input vectors (v_a, v_b) according to an adequate scheme in a second inner cycle, wherein when treating the second pair (v_a<

64;

127>

, v_b<

64;

127>

) the treatment of the first pair (v_a<

0;

63>

, v_b<

0;

63>

) is considered,

combining the results of the treatment of the first pair (v_a<

0;

63>

, v_b<

0;

63>

) and the treatment of the second pair (v_a<

64;

127>

, v_b<

64;

127>

) to a valid output vector (v_o) every second inner cycle.

9. The method according to claim 8, wherein before treating the first pair of first halves (v_a<

0;

63>

, v_b<

0;

63>

) of two parallel input vectors (v_a, v_b) the parallel input vectors are divided into successive pairs of first (v_a<

0;

63>

, v_b<

0;

63>

) and second halves (v_a<

64;

127>

, v_b<

64;

127>

).