METHOD OF SWITCHING EXTERNAL MODELS IN AN AUTOMATED SYSTEM-ON-CHIP INTEGRATED CIRCUIT DESIGN VERIFICATION SYSTEM

• US 20080133206A1
• Filed: 01/07/2008
• Published: 06/05/2008
• Est. Priority Date: 02/01/2002
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: David W. Milton, Robert D. Herzl, Robert J. Devins
• Inventors: Milton, David W., Devins, Robert J., Herzl, Robert D.
• Granted Patent: US 7,917,348 B2
• Time in Patent Office: Days
• US Class Current: 703/15
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A system and method for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.

Claims

1. A method for verifying an integrated circuit design comprising:

providing a simulation model of an I/O controller connected to one or more simulated I/O cores, said I/O cores part of said integrated circuit design;

providing a simulation model of an external memory mapped test device having a simulated switch for selectively connecting one or more of said I/O cores to corresponding simulated one or more I/O driver models;

providing a simulated bus for transferring signals between said I/O controller and said switch;

providing a test operating system for controlling said switch; and

simulating said integrated circuit design by running a test case on said test operating system.

2. The method of claim 1, further including:

distributing said external memory mapped test device and said switch among a plurality of simulated external memory mapped test device modules, each module containing a portion of said switch and connected to one of said I/O driver models.

3. The method of claim 1, further including:

providing said external memory mapped test with a simulated address register for setting said switch and controlling said I/O driver models.

4. The method of claim 1 further including:

providing a simulated embedded processor in said integrated circuit design for running said test operating system.

5. The method of claim 2, further including:

providing each external memory mapped test device module with a simulated address register for setting said portion of said switch and controlling said one or more I/O driver models.

6. The method of claim 2, further including:

providing each integrated circuit design with a simulated embedded processor for running said test operating system.

7. The method of claim 1, further including:

distributing said external memory mapped test device and said switch among a plurality of simulated external memory mapped test device modules, each module containing a portion of said switch and connected to one of said one or more I/O driver models; and

providing an simulated additional external memory mapped test device module directly connected to simulated one or more additional I/O driver models, each additional I/O driver model directly connected to a simulated additional I/O core, each additional I/O core part of said integrated circuit design.

8. A method, comprising:

loading code representing an integrated circuit design into a memory unit, said integrated circuit design including simulated I/O cores, a simulated memory controller, a simulated I/O controller, a simulated bus system and a simulated processor, said simulated I/O cores and said simulated I/O controller connected to said simulated processor by said simulated system bus;

loading into said memory unit, code representing (i) an external memory model connected to a simulated external memory mapped test device and to said simulated memory controller, (ii) one or more first external I/O driver models connected between said simulated I/O cores and said simulated external memory mapped test device and (iii) one or more second external I/O driver models connected between a simulated switch of said simulated external memory mapped test device and said I/O controller, said simulated switch programmably connectable to said one or more second external I/O driver models in response to computer-executable instructions in a test case, all said connections of (i), (ii) and (iii) by corresponding simulated I/O buses;

loading said test case into said processor, said test case comprising said list of computer-executable instructions for said simulated processor into said external memory model, said instructions describing selection of one or more simulated I/O cores and corresponding second external I/O models, allocation of pins of said I/O controller to selected simulated I/O cores and switch positions of said simulated switch to connect said corresponding second external I/O models to said I/O controller;

executing said test case on said process and allocating and connecting I/O pins of said simulated I/O controller to one or more of said simulated I/O cores, and connecting said simulated external memory mapped test device to said simulated I/O controller through said corresponding second external I/O models executing test stimuli of said test case on said simulated processor in order to generate data representing a response of said computer simulation model of said integrated circuit design to said test case; and

outputting said data representing (iv) a response of said computer simulation model of said integrated circuit design to said test case to a computer readable media or a computer, (v) displaying said data representing a response of said computer simulation model of said integrated circuit design on a computer screen, or both (iv) and (v).

9. The method of claim 8, wherein said simulated external memory mapped test device and said simulated switch are distributed among a plurality of simulated external memory mapped test device modules, each module of said plurality of simulated external memory mapped test device modules containing a portion of said simulated switch and connected to a respective second external I/O driver model of said second external I/O driver models.

10. The method of claim 9, wherein each said simulated external memory mapped test device module further includes a simulated address register.

11. The method of claim 9, wherein said simulated external memory mapped test device further includes a simulated address register.

12. The method of claim 9, wherein said simulated external memory mapped test device and said simulated switch are distributed among a plurality of simulated external memory mapped test device modules, each module of said plurality of simulated external memory mapped test device modules containing a portion of said simulated switch and connected to a respective second external I/O driver model of said one or more second external I/O driver models;

and

loading code representing an additional simulated external memory mapped test device module into said memory unit;

said loading of said test case connecting one or more additional second external I/O driver models to said additional simulated external memory mapped test device by additional simulated I/O buses; and

said loading of said test case connecting each additional second external I/O driver model to a respective additional simulated I/O core by said simulated system bus, each additional simulated I/O core comprising said model of integrated circuit design.

13. The method of claim 9, wherein said one or more simulated I/O cores are each independently selected from the group consisting of a simulated 1394 I/O core, a simulated universal asynchronous receiver transmitter core, a simulated serial core, a simulated general purpose I/O core, and a direct memory access core.