DATA TRANSFER APPARATUS WITH CONTROL OF BUSES TO OPTIMIZE DATA TRANSFER

• US 20080133814A1
• Filed: 02/08/2008
• Published: 06/05/2008
• Est. Priority Date: 10/01/2001
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Kenichi Kawaguchi
• Inventors: Kawaguchi, Kenichi
• Granted Patent: US 7,516,262 B2
• Time in Patent Office: Days
• US Class Current: 710/309
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4031 with arbitration
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: G06F 2213/0024 Peripheral component interconnect [PCI]

Abstract

A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a data FIFO, and a register block. The register block, which can be written by the master, includes two registers corresponding to the primary and secondary buses. Relay information showing the number of entries of data to be relayed from the target to the master is registered in a register corresponding to a bus to which the target is connected. In a read transaction, the primary bus interface or the secondary bus interface reads data from the target until data of the amount shown by the registered relay information is stored in the data FIFO.

Claims

1. A data transfer apparatus comprising:

(A) a first portion in an externally-writable data storing area configured to store a first size of data to be relayed from a target device on a primary bus to a master device on a secondary bus;

(B) a second portion in the externally-writable data storing area configured to store a second size of data to be relayed from a target device on the secondary bus to a master device on the primary bus;

(C) a first data storage;

(D) a second data storage;

(E) a primary bus master block configured to read data from a target device on the primary bus and write the data into the first data storage while occupying the primary bus until the size of data stored in the first data storage reaches the first size of data; and

(F) a secondary bus master block configured to read data from a target device on the secondary bus and write the data into the second data storage while occupying the secondary bus until the size of data stored in the second data storage reaches the second size of data.

2. A data transfer apparatus of claim 1, further comprising:

(G) a bus arbiter,

wherein the bus arbiter selects a bus master device on the secondary bus among devices on the secondary bus including the data transfer apparatus.

3. A data transfer apparatus of claim 1, further comprising:

(H) a controller,

wherein the controller writes data of a data write transaction on the externally-writable date storing area when the address of the data write transaction indicates the address of the externally-writable data storing area.

4. A data transfer apparatus of claim 3,

wherein the controller reads data on the externally-writable data storing area when the address of a data read transaction indicates the address of the externally-writable data storing area.

5. A data transfer apparatus of claim 2, further comprising:

(H) a controller,

wherein the controller writes data of a data write transaction on the externally-writable data storing area when the address of the data write transaction indicates the address of the externally-writable data storing area.

6. A data transfer apparatus of claim 5,

wherein the controller reads date on the externally-writable data storing area when the address of a data read transaction indicates the address of the externally-writable data storing area.

7. A data transfer apparatus of claim 1, further comprising:

(H) a primary bus target block,

wherein the primary bus target block responds to a read cycle on the primary bus with retry when the data transfer apparatus is not ready for responding with the data to be read and stores the address driven on the primary bus.

8. A data transfer apparatus of claim 1, further comprising:

(H) a secondary bus target block,

wherein the secondary bus target block responds to a read cycle on the secondary bus with retry when the data transfer apparatus is not ready for responding with the data to be read and stores the address driven on the secondary bus.