ERROR CORRECTION IN MEMORY DEVICES

• US 20080133994A1
• Filed: 12/05/2006
• Published: 06/05/2008
• Est. Priority Date: 12/05/2006
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Oh, Jong-Hoon
• Granted Patent: US 7,861,138 B2
• Time in Patent Office: Days
• US Class Current: 714/746
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence

Abstract

Embodiments of the invention generally provide a method and apparatus for correcting errors in a memory device. In one embodiment, the method includes receiving a read command and a read address for the read command and reading data from a first location of the memory device corresponding to the read address. The method also includes reading error correction information corresponding to the read address. If the error correction information indicates an error in the data, the error in the data is corrected to produce corrected data and the corrected data is output from the memory device. The corrected data is also written back to a second location in the memory device corresponding to the read address.

Claims

1. A method of correcting errors in a memory device, comprising:

receiving a read command and a read address for the read command;

reading data from a first location of the memory device corresponding to the read address;

reading error correction information corresponding to the read address;

producing corrected data when the error correction information indicates an error in the data; and

writing the corrected data to a second location in the memory device corresponding to the read address.

2. The method of claim 1, wherein the first location and the second location are the same location.

3. The method of claim 1, wherein the memory device is a dynamic random access memory device.

4. The method of claim 1, wherein reading error correction information corresponding to the read address comprises:

reading the error correction information from a location in a memory array of the memory device corresponding to the read address.

5. The method of claim 1, wherein the error correction information provides single bit error correction for a group of four data addresses in the memory device.

6. The method of claim 5, wherein the memory device is configured to provide write accesses for single data addresses.

7. A method of correcting errors in a memory device, comprising:

receiving a read command and a read address for the read command;

reading data from a location in a memory array of the memory device corresponding to the read address;

reading error correction information corresponding to the read address;

producing corrected data when the error correction information indicates an error in the data; and

writing the corrected data to the location in the memory array of the memory device corresponding to the read address.

8. The method of claim 7, wherein the memory device is a dynamic random access memory device.

9. The method of claim 7, wherein the memory array includes a first port and a second port, wherein reading the data from the location in the memory array comprises reading the data from the first port, and wherein writing the corrected data to the location in the memory array comprises writing the corrected data to the second port.

10. The method of claim 7, wherein reading error correction information corresponding to the read address comprises:

reading the error correction information from the location in the memory array corresponding to the read address.

11. The method of claim 7, wherein the error correction information provides single bit error correction for a group of four data addresses in the memory array.

12. The method of claim 11, wherein the memory device is configured to provide write accesses for single data addresses in the memory array.

13. A memory device, comprising:

a memory array;

circuitry configured to;

receive a read command and a read address for the read command;

retrieve data from a location in the memory array corresponding to the read address;

read error correction information corresponding to the read address;

produce corrected data when the error correction information indicates an error in the data; and

write the corrected data to the location in the memory array of the memory device corresponding to the read address.

14. The memory device of claim 13, wherein the memory device is a dynamic random access memory device.

15. The memory device of claim 13, wherein the memory array includes a first port and a second port, and wherein the circuitry is configured to read the data from the first port and write the corrected data back to the location in the memory array via the second port.

16. The memory device of claim 13, wherein reading error correction information corresponding to the read address comprises:

reading the error correction information from the location in the memory array corresponding to the read address.

17. The memory device of claim 13, wherein the error correction information provides single bit error correction for a group of four data addresses in the memory array.

18. The memory device of claim 17, wherein the memory device is configured to provide write accesses for single data addresses in the memory array.

19. A method of correcting errors in a memory device, comprising:

receiving a read command and a read address for the read command;

reading data from a first location in a memory array of the memory device corresponding to the read address;

reading error correction information corresponding to the read address;

producing corrected data when the error correction information indicates an error in the data;

storing the corrected data back to a memory storage location of the memory device separate from the memory array; and

storing the read address to an address storage location of the memory device associated with the memory storage location of the memory device to indicate the read address of the corrected data.

20. The method of claim 19, wherein the memory array comprises dynamic random access memory, and wherein the memory storage location comprises static random access memory.

21. The method of claim 19, further comprising:

receiving an access command and an access address for the access command; and

in response to receiving the access command;

determining if the access address matches the read address stored in the address storage location;

using the access command to access the corrected data stored in the memory storage location if the access address matches the read address; and

using the access command to access the first location in the memory array of the memory device if the access address does not match the read address.

22. The method of claim 19, wherein the address storage location is a register.

23. The method of claim 19, wherein reading error correction information corresponding to the read address comprises:

reading the error correction information from the location in the memory array corresponding to the read address.

24. The method of claim 19, wherein the error correction information provides single bit error correction for a group of four data addresses in the memory array.

25. The method of claim 24, wherein the memory device is configured to provide write accesses for single data addresses in the memory array.

26. The method of claim 19, wherein the address storage location of the memory device comprises non-volatile memory configured to store the read address.

27. A memory device, comprising:

a memory array;

circuitry configured to;

receive a read command and a read address for the read command;

retrieve data from a first location in the memory array corresponding to the read address;

read error correction information corresponding to the read address;

produce corrected data when the error correction information indicates an error in the data;

store the corrected data back to a memory storage location of the memory device separate from the memory array; and

store the read address to an address storage location of the memory device associated with the memory storage location of the memory device to indicate the read address of the corrected data.

28. The memory device of claim 27, wherein the memory array comprises dynamic random access memory, and wherein the memory storage location comprises static random access memory.

29. The memory device of claim 27, wherein the circuitry is further configured to:

receive an access command and an access address for the access command; and

in response to receiving the access command;

determine if the access address matches the read address stored in the address storage location;

use the access command to access the corrected data stored in the memory storage location if the access address matches the read address; and

use the access command to access the first location in the memory array of the memory device if the access address does not match the read address.

30. The memory device of claim 27, wherein the address storage location is a register.

31. The memory device of claim 27, wherein reading error correction information corresponding to the read address comprises:

reading the error correction information from the location in the memory array corresponding to the read address.

32. The memory device of claim 27, wherein the error correction information provides single bit error correction for a group of four data addresses in the memory array.

33. The memory device of claim 32, wherein the memory device is configured to provide write accesses for single data addresses in the memory array.

34. The memory device of claim 27, wherein the address storage location of the memory device comprises non-volatile memory configured to store the read address.