Printed wiring board having plural solder resist layers and method for production thereof

• US 20080135279A1
• Filed: 11/13/2007
• Published: 06/12/2008
• Est. Priority Date: 12/11/2006
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Ishido, Kiminori
• Application Number:
  US11/984,037
• Publication Number:
  US 20080135279A1
• Time in Patent Office: Days
• US Class Current: 174/255
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13021 the bump connector being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H05K 2201/10674 Flip chip
• CPC Class Codes: H05K 2203/0588 Second resist used as pattern over first resist
• CPC Class Codes: H05K 2203/0594 Insulating resist or coating with special shaped edges
• CPC Class Codes: H05K 3/3452 Solder masks
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

A printed wiring board includes: a substrate main body; a solder resist layer provided on the substrate main body and having a first opening in which a part of the solder bump is formed; and a solder resist layer provided on the solder resist layer and having a second opening through which the solder bump is formed. The shape of the second opening is non-analogous to the shape of the first opening when viewed as plane-wise.

Claims

1. A printed wiring board, comprising:

a substrate main body;

a first solder resist layer which is provided on the substrate main body and comprises a first opening in which a part of the solder bump is buried; and

a second solder resist layer which is provided on the first solder resist layer and comprises a second opening through which the solder bump extends,

wherein a shape of the second opening is non-analogous to a shape of the first opening when viewed as plane-wise.

2. The printed wiring board according to claim 1, wherein said second solder resist layer comprises a first surface attached to the first solder resist layer and a second surface opposed to said first surface, said first surface having an area smaller than an area of said second surface.

3. The printed wiring board according to claim 1, wherein an angle of a side surface of the second solder resist layer with respect to the first solder resist layer is less than 90°

.

4. The printed wiring board according to claim 1, wherein the shapes of the first and second openings are circular and rectangular, respectively, when viewed plane-wise.

5. The printed wiring board according to claim 1, wherein the second solder resist layer is columnar.

6. The printed wiring board according to claim 5, wherein the second solder resist layer is arranged in a form of a zigzag lattice with the first opening when viewed plane-wise.

7. The printed wiring board according to claim 1, wherein the thickness of the second solder resist layer is in a range of 5 μ

m or more and 35 μ

m or less.

8. The printed wiring board according to claim 1, wherein the first opening is geometrically same as said second opening.

9. A method of forming a printed wiring board, comprising:

forming, on a substrate main body, a first solder resist layer including a first opening in which a part of a solder bump is buried; and

forming, on the first solder resist layer, a second solder resist layer containing a second opening through which the solder bump extends,

wherein the second opening is formed so as to have a shape which is non-analogous to a shape of the first opening when viewed plane-wise.

10. The method according to claim 9, wherein said forming the second solder resist layer comprises:

treating the second solder resist layer of a photographic development type so as to be rendered tack-free;

exposing the second solder resist layer after treatment and carrying out development for a development time in a range of two times or more and five times or less as long as a break point; and

curing the second solder resist layer after the development.

11. A printed wiring board, comprising:

a substrate main body;

a first solder resist layer which is provided on the substrate main body and comprises a first opening to form a solder bump therein; and

a second solder resist layer which is provided on the first solder resist layer and comprises a second opening to form the solder bump therein, said second opening having an other than circular structure such that the distance between an edge of said first opening and an edge of said second opening varies.

12. The printed wiring board as claimed in claim 11, wherein said second opening has rectangular shape.

13. The printed wiring board as claimed in claim 11, wherein said second opening has a shape so that said second solder resist layer constitutes a structure including a plurality of column.

14. The printed wiring board as claimed in claim 11, wherein said second opening has a polygonal shape.

15. The printed wiring board as claimed in claim 11, wherein said second opening has an oval shape.

16. The printed wiring board as claimed in claim 11, wherein said second solder resist layer comprises a first surface attached to the first solder resist layer and a second surface opposed to said first surface, said first surface having an area smaller than an area of said second surface.