METHOD OF FABRICATING THIN FILM TRANSISTOR HAVING MULTILAYER STRUCTURE AND ACTIVE MATRIX DISPLAY DEVICE INCLUDING THE THIN FILM TRANSISTOR
First Claim
1. A method of fabricating a thin film transistor, comprising:
- preparing a substrate formed of plastic;
forming a buffer insulating layer on the plastic substrate;
forming a silicon layer on the buffer insulating layer;
patterning the silicon layer to form an active layer;
forming a gate insulating layer on the active layer;
stacking a plurality of gate metal layers on the gate insulating layer;
patterning the plurality of gate metal layers; and
etching a corner region of the lowest gate metal layer formed on the gate insulating layer of the patterned gate metal layers.
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Accused Products
Abstract
Provided are a method of fabricating a multilayered thin film transistor using a plastic substrate and an active matrix display device including the thin film transistor fabricated by the method. The method includes: preparing a substrate formed of plastic; forming a buffer insulating layer on the plastic substrate; forming a silicon layer on the buffer insulating layer; patterning the silicon layer to form an active layer; forming a gate insulating layer on the active layer; stacking a plurality of gate metal layers on the gate insulating layer; patterning the plurality of gate metal layers; and etching a corner region of the lowest gate metal layer formed on the gate insulating layer of the patterned gate metal layers. Accordingly, a gate metal is formed which includes a multilayered gate metal layer and has an etched corner region, thereby reducing an electric field of the corner to reduce a leakage current of the TFT.
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Citations
6 Claims
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1. A method of fabricating a thin film transistor, comprising:
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preparing a substrate formed of plastic; forming a buffer insulating layer on the plastic substrate; forming a silicon layer on the buffer insulating layer; patterning the silicon layer to form an active layer; forming a gate insulating layer on the active layer; stacking a plurality of gate metal layers on the gate insulating layer; patterning the plurality of gate metal layers; and etching a corner region of the lowest gate metal layer formed on the gate insulating layer of the patterned gate metal layers. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification