THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURE

• US 20080135846A1
• Filed: 12/12/2007
• Published: 06/12/2008
• Est. Priority Date: 12/12/2006
• Status: Active Grant

• Current Assignee: Kla-Tencor Technologies Corporation (KLA Corporation), Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chai, Chong-Chul, Jung, Mee-Hye, SHIN, Kyoung-Ju
• Granted Patent: US 7,928,437 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A thin film transistor (“TFT”) substrate in which the size of a pixel TFT formed in a display area is reduced using a single slit mask, and the length of the channel area of a protection TFT constituting an electrostatic discharge protection circuit formed in a non-display area is formed larger than that of the pixel TFT using the same mask pattern. The TFT substrate includes a signal line and a discharge line formed on a substrate, a signal supply pad formed on one end of the signal line to supply a signal to the signal line, and an electrostatic discharge protection circuit including at least one protection TFT including a plurality of channels formed between the signal supply pad and the discharge line and/or between the signal line and the discharge line.

Claims

1. A thin film transistor substrate comprising:

a signal line and a discharge line formed on a substrate;

a signal supply pad formed on one end of the signal line to supply a signal to the signal line; and

an electrostatic discharge protection circuit including at least one protection thin film transistor having a plurality of channels formed between the signal supply pad and the discharge line and/or between the signal line and the discharge line.

2. The thin film transistor substrate of claim 1, wherein the protection thin film transistor comprises:

a first gate electrode;

a gate insulating layer covering the first gate electrode;

a first semiconductor layer and a first ohmic contact layer formed on the gate insulating layer, wherein the first semiconductor layer and a first ohmic contact layer overlap the first gate electrode;

a first source electrode and a first drain electrode formed facing each other on the first ohmic contact layer; and

at least one floating electrode formed on the first ohmic contact layer between the first source electrode and the first drain electrode.

3. The thin film transistor substrate of claim 2, wherein the signal line comprises:

a gate line supplying a gate-on voltage and a gate-off voltage; and

a data line supplying a data voltage, wherein the data line is insulated from the gate line.

4. The thin film transistor substrate of claim 3, wherein the discharge line comprises at least one of a storage signal supply line receiving a storage voltage, a test line receiving a test signal for testing the signal line, and a floating line.

5. The thin film transistor substrate of claim 4, further comprising:

a pixel thin film transistor electrically connected to the gate line and the data line; and

a pixel electrode connected to the pixel thin film transistor.

6. The thin film transistor substrate of claim 5, wherein the pixel thin film transistor comprises:

a second gate electrode connected to the gate line;

the gate insulating layer covering the second gate electrode;

a second source electrode connected to the data line;

a second drain electrode formed facing the second source electrode;

a second semiconductor layer formed between the second source electrode, the second drain electrode and the gate insulating layer, to form a second channel; and

a second ohmic contact layer formed between the second semiconductor layer and the second source electrode, and between the second semiconductor layer and the second drain electrode.

7. The thin film transistor substrate of claim 6, wherein the sum of lengths of the plurality of channels formed in the protection thin film transistor is greater than a channel length of the pixel thin film transistor.

8. The thin film transistor substrate of claim 7, further comprising:

a gate driving unit integrated into the substrate to provide the gate-on voltage and the gate-off voltage to the gate line;

the signal supply pad providing a driving signal to the gate driving unit;

the discharge line formed between the signal supply pad and the gate driving unit; and

the electrostatic discharge protection circuit formed between the signal supply pad and the discharge line.

9. A method of manufacturing a thin film transistor substrate, the method comprising:

forming a first conductive layer on a substrate;

forming a first gate electrode, a discharge line and a gate pad electrode in a non-display area, and a gate pattern including a gate line connected to the gate pad electrode and a second gate electrode connected to the gate line in a display area by patterning the first conductive layer;

stacking a gate insulating layer, a semiconductor layer, an ohmic contact layer, and a second conductive layer on the gate pattern;

forming a data pad electrode, a first source electrode, a first drain electrode facing the first source electrode, at least one floating electrode between the first source electrode and the second drain electrode, and a discharge line in the non-display area, and a data pattern including a data line connected to the data pad electrode, a second source electrode connected to the data line and a second drain electrode facing the second source electrode in the display area by patterning the second conductive layer; and

forming a protection thin film transistor including a plurality of channels by etching the ohmic contact layer between the first source electrode, the first drain electrode and the floating electrode, and then forming a pixel thin film transistor having a single channel by etching the ohmic contact layer between the second source electrode and the second drain electrode.

10. The method of claim 9, wherein forming the data pattern comprises:

forming a photoresist on the second conductive layer;

exposing the photoresist through a mask including a blocking area formed in areas where the first and second source electrodes, the first and second drain electrodes, the data line and the floating electrode are to be formed, a single slit area formed in areas where channels are to be formed, and a transmission area formed in the remaining area;

forming a photoresist pattern in an area corresponding to the blocking area, a remaining photoresist pattern in an area corresponding to the single slit area by developing the photoresist;

etching the substrate on which the photoresist pattern and the remaining photoresist pattern are formed;

exposing the second conductive layer corresponding to the channel area by ashing the remaining photoresist; and

forming the first and second source electrodes, the first and second drain electrodes, the data line, the discharge line and the floating electrode by etching the substrate on which the photoresist pattern is formed.

11. The method of claim 10, wherein the single slit area in the display area has a slit width the same as that of the single slit area in the non-display area.

12. The method of claim 11, wherein the slit width is in a range of about 1.9 μ

m to about 2.6 μ

m.

13. The method of claim 12, wherein the channel length of the non-display area is greater than that of the display area.

14. The method of claim 13, further comprising:

forming a passivation layer protecting the protection thin film transistor and the pixel thin film transistor; and

forming a pixel electrode connected to the pixel thin film transistor, a gate pad connected to the gate pad electrode, and a data pad connected to the data pad electrode on the passivation layer.

15. The method of claim 14, wherein at least one of forming the gate pattern and forming the data pattern further comprises forming a discharge line connected to the protection thin film transistor.

16. The method of claim 15, wherein at least one of forming the gate pattern and forming the data pattern further comprises forming a test line providing a test signal to the gate line and the data line, respectively.

17. The method of claim 16, further comprising forming the protection thin film transistor between the test line and the gate pad or between the test line and the data pad.

18. The method of claim 9, further comprising:

forming a gate driving unit integrated into the substrate to provide a gate-on voltage and a gate-off voltage to the gate line;

forming a signal supply line providing a driving signal to the gate driving unit; and

forming a signal supply pad on one end of the signal supply line to receive the driving signal.

19. The method of claim 18, further comprising:

forming a discharge line between the signal supply pad and the gate driving unit; and

forming a protection thin film transistor connected between the signal supply line and the discharge line.