Semiconductor Device and Method of Manufacturing the Same

• US 20080135870A1
• Filed: 11/01/2007
• Published: 06/12/2008
• Est. Priority Date: 11/02/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Semiconductor Company Limited (ON Semiconductor Corporation), Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Kameyama, Kojiro, Okada, Kikuo
• Granted Patent: US 7,659,576 B2
• Time in Patent Office: Days
• US Class Current: 257/133
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT

Abstract

A punch-through type IGBT generally has a thick p⁺⁺-type collector layer. Therefore, the FWD need be externally attached to the IGBT when the IGBT is used as a switching element in an inverter circuit for driving a motor load, and thus the number of processes and components increases. In the invention, trenches are formed penetrating through a collector layer and reaching a buffer layer. A collector electrode is formed in the trenches, too. With this structure, a current path is formed between an emitter electrode and the collector electrode without through the collector layer and functions as the FWD.

Claims

1. A semiconductor device comprising:

a collector layer of a first general conductivity type;

a drift layer of a second general conductivity type disposed on a front surface of the collector layer;

a base region of the first general conductivity type formed in the drift layer;

an emitter region of the second general conductivity type formed in the base region;

a gate insulation film disposed on the base region so as to cover a portion of the base region between the drift layer and the emitter region;

a gate electrode disposed on the gate insulation film;

an emitter electrode connected to the emitter region; and

a collector electrode disposed on a back surface of the collector layer and comprising branching portions penetrating through the collector layer.

2. The semiconductor device of claim 1, further comprising a buffer layer of the second general conductivity type disposed between the collector layer and the drift layer and having a higher impurity concentration than the drift layer.

3. The semiconductor device of claim 2, wherein the branching portions terminate in the buffer layer.

4. The semiconductor device of claim 1, wherein the branching portions are formed as trenches.

5. The semiconductor device of claim 4, wherein the collector electrode fills the trenches.

6. The semiconductor device of claim 1, wherein the branching portions comprise tapered sidewalls.

7. The semiconductor device of claim 1, wherein the collector electrode comprises copper.

8. The semiconductor device of claim 1, wherein the collector electrode comprises polysilicon.

9. The semiconductor device of claim 1, wherein one of the branching portions is disposed under the base region between the gate electrode and another gate electrode.

10. A semiconductor device comprising:

a collector layer of a first general conductivity type;

a drift layer of a second general conductivity type disposed on a front surface of the collector layer;

a base layer of the first general conductivity type disposed on the drift layer;

a trench penetrating through the base layer so as to reach the drift layer;

a gate insulation film disposed on an inner wall of the trench;

a gate electrode disposed in the trench so as to cover the gate insulation film;

an emitter region of the second general conductivity type formed in the base layer and adjacent the trench;

an emitter electrode connected to the emitter region; and

a collector electrode disposed on a back surface of the collector layer and comprising branching portions penetrating through the collector layer.

11. The semiconductor device of claim 10, further comprising a buffer layer of the second general conductivity type disposed between the collector layer and the drift layer and having a higher impurity concentration than the drift layer.

12. The semiconductor device of claim 11, wherein the branching portions terminate in the buffer layer.

13. The semiconductor device of claim 10, wherein the branching portions are formed as trenches.

14. The semiconductor device of claim 13, wherein the collector electrode fills the trenches.

15. The semiconductor device of claim 10, wherein the branching portions comprise tapered sidewalls.

16. The semiconductor device of claim 10, wherein the collector electrode comprises copper.

17. The semiconductor device of claim 10, wherein the collector electrode comprises polysilicon.

18. The semiconductor device of claim 10, wherein one of the branching portions is disposed under the base layer between the gate electrode and another gate electrode.

19. A method of manufacturing a semiconductor device, comprising:

providing a collector layer of a first general conductivity type;

forming a drift layer of a second general conductivity type on a front surface of the collector layer;

forming base regions of the first general conductivity type in the drift layer;

forming emitter regions of the second general conductivity type in the base regions;

forming a gate insulation film on the base regions so as to cover portions of the base regions between the drift layer and the emitter regions;

forming gate electrodes on the gate insulation film;

forming an emitter electrode so as to be connected to the emitter regions;

forming openings from a back surface of the collector layer so that the openings penetrate through the collector layer; and

forming a collector electrode on the back surface of the collector layer so as to fill the openings at least partially.

20. The method of claim 19, wherein the openings are formed under base regions between the gate electrodes.

21. A method of manufacturing a semiconductor device, comprising:

providing a collector layer of a first general conductivity type;

forming a drift layer of a second general conductivity type on a front surface of the collector layer;

forming a base layer of the first general conductivity type on the drift layer;

forming trenches penetrating through the base layer so as to reach the drift layer;

forming a gate insulation film on an inner wall of each of the trenches;

forming a gate electrode in each of the trenches so as to cover a corresponding gate insulation film;

forming emitter regions of the second general conductivity type in the base layer and adjacent the trenches;

forming an emitter electrode connected to the emitter regions;

forming openings from a back surface of the collector layer so that the openings penetrate through the collector layer; and

forming a collector electrode on the back surface of the collector layer so as to fill the openings at least partially.

22. The method of claim 21, wherein the openings are formed under base layer between the gate electrodes.