Structure and Method for Forming a Planar Schottky Contact

• US 20080135889A1
• Filed: 05/11/2007
• Published: 06/12/2008
• Est. Priority Date: 12/06/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Session, Fred
• Granted Patent: US 7,732,842 B2
• Time in Patent Office: Days
• US Class Current: 257/284
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A monolithically integrated trench FET and Schottky diode includes a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer. A trench in the Schottky region includes a dielectric layer lining the trench sidewalls, and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench. An interconnect layer electrically contacts the semiconductor layer in the Schottky region so as to form a Schottky contact with the semiconductor layer.

Claims

1. A monolithically integrated trench FET and Schottky diode, comprising:

a plurality of trenches extending into a FET region and a Schottky region of a semiconductor layer, a trench in the Schottky region having a dielectric layer lining the trench sidewalls and a conductive electrode having a top surface that is substantially coplanar with a top surface of the semiconductor layer adjacent the trench; and

an interconnect layer electrically contacting the semiconductor layer in the Schottky region so as to form a Schottky contact with the semiconductor layer.

2. The monolithically integrated trench FET and Schottky diode of claim 1 wherein a trench in the FET region includes a dielectric layer lining the trench sidewalls and a conductive electrode, and wherein the interconnect layer electrically contacts the conductive electrode in the trench in the Schottky region but is electrically insulated from the conductive electrode in the trench in the FET region.

3. The monolithically integrated trench FET and Schottky diode of claim 1 wherein a surface of the semiconductor layer in the Schottky region is lower relative to a surface of the semiconductor layer in the FET region.

4. The monolithically integrated trench FET and Schottky diode of claim 1 wherein a trench in the FET region includes a dielectric layer lining the trench sidewalls and a conductive electrode having a top surface that is higher than a top surface of the conductive electrode in the trench in the Schottky region.

5. The monolithically integrated trench FET and Schottky diode of claim 1 wherein the FET region comprises:

a well region extending in the semiconductor layer;

source regions in the well region adjacent the trench in the FET region, the source regions and well region being of opposite conductivity type; and

heavy body region in the well region, the heavy body region being of the same conductivity type but higher doping concentration than the well region,

wherein the interconnect layer electrically contacts the source and heavy body regions.

6. The monolithically integrated trench FET and Schottky diode of claim 5 wherein the trench FET is a trench MOSFET, the semiconductor layer comprising an epitaxial layer extending over a substrate, the epitaxial layer having a lower doping concentration than the epitaxial layer, the well region extending in the epitaxial layer and having a conductivity type opposite that of the epitaxial layer and the substrate.

7. The monolithically integrated trench FET and Schottky diode of claim 5 wherein the trench FET is a trench IGBT, the semiconductor layer comprising an epitaxial layer extending over a substrate, the epitaxial layer having a lower doping concentration than the epitaxial layer, the well region extending in the epitaxial layer and having a conductivity type opposite that of the epitaxial layer, and the well region and the substrate having the same conductivity type.

8. The monolithically integrated trench FET and Schottky diode of claim 1 wherein a trench in the FET region includes:

a shield dielectric layer lining lower sidewalls and bottom of the trench;

a shield electrode disposed in a bottom portion of the trench;

an inter-electrode dielectric layer over the shield electrode;

a gate dielectric layer lining upper trench sidewalls, the gate dielectric layer being thinner than the shield dielectric layer; and

a gate electrode over the inter-electrode dielectric layer.

9. The monolithically integrated trench FET and Schottky diode of claim 8 wherein the trench in the Schottky region includes only one conductive electrode.

10. The monolithically integrated trench FET and Schottky diode of claim 1 wherein each of the plurality of trenches in the FET region and the Schottky diode region includes:

a shield dielectric layer lining lower sidewalls and bottom of the trench;

a shield electrode disposed in a bottom portion of the trench;

an inter-electrode dielectric layer over the shield electrode;

a gate dielectric layer lining upper trench sidewalls, the gate dielectric layer being thinner than the shield dielectric layer; and

a gate electrode over each inter-electrode dielectric layer.

11. The monolithically integrated trench FET and Schottky diode of claim 1 wherein a trench in the FET region includes:

a dielectric layer lining the trench sidewalls and bottom, the dielectric layer being thicker along the trench bottom than along the trench sidewalls; and

a recessed gate electrode.

12. A semiconductor structure, comprising:

a first trench in a first region of a semiconductor layer, the first trench having a conductive electrode therein, wherein a top surface the conductive electrode is recessed relative to a top surface of the first region of the semiconductor layer; and

a second trench in a second region of the semiconductor layer, the second trench having a conductive electrode therein, wherein the conductive electrode in the second trench has a top surface that is substantially coplanar with a top surface of the second region of the semiconductor layer,

wherein a top surface of the first region of the semiconductor layer is higher than a top surface of the second region of the semiconductor layer.

13. The semiconductor of claim 12 wherein the first region of the semiconductor layer houses a trench FET and the second region of the semiconductor layer houses a rectifier.

14. A method of forming a monolithically integrated trench FET and Schottky diode, the method comprising:

forming a plurality of trenches in a FET region and a Schottky region of a semiconductor layer;

forming a recessed conductive electrode in each trench; and

forming a contact opening in the Schottky region by removing at least a portion of the semiconductor layer and a portion of a recessed conductive electrode in a trench so that a top surface of the recessed conductive electrode and a top surface of the semiconductor layer in the Schottky region are substantially coplanar.

15. The method of claim 14 further comprising:

after the step of forming a contact opening, forming an interconnect layer electrically contacting surfaces of the semiconductor layer so as to form a Schottky contact with the semiconductor layer.

16. The method of claim 15 wherein the interconnect layer is formed so as to electrically contact the recessed conductive electrode in one or more trenches in the Schottky region but is electrically insulated from the recessed conductive electrode in one or more trenches in the FET region.

17. The method of claim 14 wherein after the step of forming a contact opening results in a surface of the semiconductor layer in the Schottky region being lower relative to a surface of the semiconductor layer in the FET region.

18. The method of claim 14 wherein after the step of forming a contact opening, a top surface of a recessed conductive electrode in a trench in the FET region is higher than a top surface of a recessed conductive electrode in a trench in the Schottky region.

19. The method of claim 14 further comprising:

prior to the step of forming a contact opening, forming a dielectric layer over the semiconductor layer,

wherein the step of forming a contact opening further includes removing a portion of the dielectric material.

20. The method of claim 19 wherein the portion of the dielectric layer, the at least a portion of the semiconductor layer and the portion of a conductive electrode in a trench are all removed using an etch process that etches the dielectric layer and the semiconductor substrate at substantially the same rate.

21. The method of claim 19 wherein the portion of the dielectric layer, the at least a portion of the semiconductor layer and the portion of a conductive electrode in a trench are all removed using an etch process that has low selectivity between the dielectric layer and the semiconductor layer.

22. The method of claim 19 further comprising:

prior to the step of forming a contact opening;

forming a protective layer over the dielectric layer; and

removing at least a portion of the protective layer to define the contact opening.

23. The method of claim 20 further comprising:

prior to the step of forming a protective layer, forming a source contact opening in a portion of the dielectric layer that extends in the FET region.

24. The method of claim 14 further comprising:

forming a well region in the FET region of the semiconductor layer;

forming source regions in the well region adjacent a trench in the FET region, the source regions and the well region being of opposite conductivity type; and

forming a heavy body region in the well region, the heavy body region being of the same conductivity type but higher doping concentration than the well region.

25. The method of claim 14 further comprising:

forming a shield dielectric layer lining lower sidewalls and bottom of a first trench in the FET region;

forming a shield electrode disposed in a bottom portion of the first trench;

forming a gate dielectric layer lining upper trench sidewalls of the first trench, the gate dielectric layer being thinner than the shield dielectric layer; and

forming a gate electrode over the shield electrode.

26. The method of claim 14 further comprising:

forming a shield dielectric layer lining lower sidewalls and bottom of each of a first trench in the FET region and a second trench in the Schottky region;

forming a shield electrode disposed in a bottom portion of each of the first and second trenches;

forming a gate dielectric layer lining upper sidewalls of each of the first and second trenches, the gate dielectric layer being thinner than the shield dielectric layer; and

forming a gate electrode over the shield electrode.

27. A method of forming a semiconductor structure, comprising:

forming a plurality of trenches in a semiconductor layer;

forming a dielectric layer lining the trench sidewalls and bottom;

forming a conductive electrode in each trench;

forming a dielectric layer over the semiconductor layer;

forming a contact opening by removing a portion of the dielectric layer, a portion of the semiconductor layer and a portion of each of one or more conductive electrodes in the plurality of trenches so that a top surface of the one or more conductive electrodes and a top surface of the semiconductor layer in the contact opening are substantially coplanar; and

forming an interconnect layer electrically contacting the one or more conductive electrodes and the semiconductor layer through the contact opening such that the interconnect layer forms a Schottky contact with the semiconductor layer.

28. The method of claim 27 wherein the portion of the dielectric layer, the portion of the semiconductor layer and the portion of each of the one or more conductive electrodes are all removed using an etch process that etches the dielectric layer and the semiconductor substrate at substantially the same rate.

29. The method of claim 27 wherein the portion of the dielectric layer, the portion of the semiconductor layer and the portion of each of one or more conductive electrodes are all removed using an etch process that has low selectivity between the dielectric layer and the semiconductor layer.