Electronic device and method of manufacturing the same, chip carrier, circuit board, and electronic instrument

• US 20080136046A1
• Filed: 11/30/2007
• Published: 06/12/2008
• Est. Priority Date: 03/13/2003
• Status: Active Grant

• Current Assignee: 138 East LCD Advancements Limited (Vector Capital Corporation)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Hashimoto, Nobuaki
• Granted Patent: US 7,611,925 B2
• Time in Patent Office: Days
• US Class Current: 257/783
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/24998 Reinforcing structures, e.g. ramp-like support
• CPC Class Codes: H01L 2224/25175 Parallel arrangements
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/76155 Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/82007 involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting a build-up interconnect during or after the bonding process
• CPC Class Codes: H01L 2224/82102 using jetting, e.g. ink jet
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

An external terminal is formed on an interconnect pattern formed on a substrate by using a soldering material. Subsequently, a chip component having an electrode is mounted on the substrate. An interconnect for electrically connecting the electrode and the interconnect pattern is formed at a temperature lower than a melting point of the soldering material.

Claims

1. A method of manufacturing an electronic device, the method comprising:

mounting a chip component above a substrate face up with an adhesive disposed between the substrate and the chip component, the chip component having an electrode on a first surface of the chip component opposite to a second surface facing the substrate;

forming an insulating section adjacent to the chip component by applying a force between the substrate and the chip component so that a portion of the adhesive is pressed out to a region adjacent to the chip component, the portion of the adhesive having a top higher from the substrate than the first surface, the insulating section formed of the portion of the adhesive; and

forming an interconnect on the insulating section from the electrode to an interconnect pattern formed on the substrate for electrically connecting the electrode and the interconnect pattern.

2. The method of manufacturing an electronic device as defined by claim 1,

wherein the interconnect is formed of a dispersant including electrically conductive particles.

3. The method of manufacturing an electronic device as defined by claim 2,

wherein the forming of the interconnect includes ejecting the dispersant including the electrically conductive particles over the insulating section and the interconnect pattern.

4. The method of manufacturing an electronic device as defined by claim 1, further comprising:

forming an external terminal on the interconnect pattern formed on the substrate,

wherein the forming of the interconnect is performed at a temperature lower than a melting point of the external electrode.

5. The method of manufacturing an electronic device as defined by claim 1, the forming of the interconnect being performed by inkjet.

6. The method of manufacturing an electronic device as defined by claim 1,

wherein the chip component is a semiconductor element.

7. An electronic device, comprising:

a substrate;

an interconnect pattern that is formed on the substrate;

a chip component that is mounted above the substrate, the chip component including a first surface and a second surface, the first surface being opposite to the second surface, the second surface facing the substrate;

an electrode that is formed on the first surface;

an adhesive that is disposed between the substrate and the chip component, the adhesive including a first portion and a second portion, the first portion being disposed between the substrate and the chip component, the second portion being disposed adjacent to the chip component, the second portion having a top higher from the substrate than the first surface; and

an interconnect that extends from the electrode to the interconnect pattern, a first part of the interconnect being in touch with the second portion.

8. The electronic device as defined by claim 7, the interconnect being formed of a dispersant including electrically conductive particles

9. The electronic device as defined by claim 7, further comprising:

an external terminal that is formed on the interconnect pattern.

10. The electronic device as defined by claim 7, the second portion including a convex surface that draws a curve as seen in a section perpendicular to the first surface.

11. The electronic device as defined by claim 7, the second portion including a step-shaped portion.