Apparatus, system and method for testing electronic elements

• US 20080136431A1
• Filed: 02/13/2008
• Published: 06/12/2008
• Est. Priority Date: 03/25/2005
• Status: Active Grant

• Current Assignee: Vishay General Semiconductor LLC (Vishay Intertechnology Incorporated)
• Original Assignee: Vishay General Semiconductor LLC (Vishay Intertechnology Incorporated)
• Inventors: Wu, Shyan-l, Hsu, Chin-Chen, Lin, Yi-Li, Li, Kuang-Jung
• Granted Patent: US 7,671,611 B2
• Time in Patent Office: Days
• US Class Current: 324/754
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence

Abstract

An electronic element testing apparatus for use with a number of probes. Each probe has a lower pole and an upper pole. The apparatus includes: a first plate having a first side and a second side, the first side having an array of lower pole regions disposed thereabout, each lower pole region configured to receive a lower pole of a probe; and a plurality of signal conductor regions disposed proximate the array of lower pole regions, each signal conductor region arranged to provide a non-cable electrical path between a lower pole region and a switching circuit. The switching circuits are operable to sequentially connect each electronic element to a testing circuit via the upper and lower poles.

Claims

1. A system for testing a number of electronic elements using a number of probes, each probe having a lower pole and an upper pole, the system comprising:

a testing apparatus, comprising

a first plate having a first side and a second side, the first side having an array of lower pole regions disposed thereabout, each lower pole region configured to receive a lower pole of a probe, and

a plurality of signal conductor regions disposed proximate the array of lower pole regions, each signal conductor region arranged to provide a non-cable electrical path between a lower pole region and a switching circuit;

a computer-readable storage medium; and

a processor responsive to the testing apparatus, to the computer-readable storage medium, and to a computer program, the computer program, when loaded into the processor, operative to

control the testing apparatus to produce test results by causing the switching circuits to sequentially connect each electronic element to a testing circuit via the upper and lower poles of a probe, when lower poles are disposed at at least some of the lower pole regions, when each lower pole contacts a first terminal region of an electronic element, when an upper pole, responsive to a complementary lower pole, contacts a second terminal region of the electronic element, and when each signal conductor region provides a non-cable electrical path between a lower pole region and a switching circuit, and

control storage of the test results in the computer-readable storage medium.

2. The system according to claim 1, wherein the computer-readable storage medium comprises a memory map, the memory map having a number of memory zones, each memory zone corresponding to a predetermined range of test results, each memory zone having a number of test result areas corresponding to the number of electronic elements, the computer program operative, based on the test results, to control storage of a particular test result in a particular memory zone and test result area of the memory map.

3. The system according to claim 2, further comprising:

a number of sorting receptacles arranged to receive electronic elements from the testing apparatus, the number of sorting receptacles corresponding to the number of memory zones, the computer program further operative to cause substantially simultaneous placement of the electronic elements into a particular sorting receptacle associated with a particular memory zone based on contents of the test result areas of the particular memory zone.

4. A method for sorting a number of electronic elements into a plurality of sorting receptacles using a testing apparatus and a number of probes, each probe having a lower pole and an upper pole, the testing apparatus comprising

a first plate having a first side and a second side, the first side having an array of lower pole regions disposed thereabout, each lower pole region configured to receive a lower pole of a probe, and

a plurality of signal conductor regions disposed proximate the array of lower pole regions, each signal conductor region arranged to provide a non-cable electrical path between a lower pole region and a switching circuit, the method comprising:

when lower poles are disposed at at least some of the lower pole regions, arranging for establishment of electrical contact between each lower pole and a first terminal region of an electronic element;

arranging for establishment of electrical contact between each of a plurality of upper poles and a second terminal region of the electronic element, each upper pole complementary to a lower pole;

arranging for establishment of a non-cable electrical path between each lower pole and a switching circuit;

testing the electronic elements by causing the switching circuits to sequentially connect each electronic element to a testing circuit via the upper and lower poles, the testing circuit producing a set of test results;

arranging for storage of the set of test results in a memory; and

based on the set of test results, arranging for substantially simultaneous placement of each electronic element belonging in a first sorting receptacle into the first sorting receptacle; and

after the step of placing each electronic element belonging in the first sorting receptacle into the first sorting receptacle, based on the set of test results, arranging for substantially simultaneous placement of each electronic element belonging in a second sorting receptacle into the second sorting receptacle.

5. The method according to claim 4, wherein the step of arranging for storage of the set of test results in a memory further comprises:

locating a number of memory zones in the memory, each memory zone corresponding to a predetermined range of test results and having a number of test result areas corresponding to the number of electronic elements, the memory zones and the test result areas collectively comprising a memory map; and

arranging for storage of a particular test result of the set of test results in the memory map.

6. The method according to claim 5, wherein the step of arranging for storage of a particular test result of the set of test results in the memory map comprises:

after testing a particular electronic element, arranging for storage of the test result in a particular test result area of each memory zone.

7. The method according to claim 6, wherein step of arranging for storage of the test result in a particular test result area of each memory zone comprises one of setting and clearing a flag in the particular test result area of each memory zone.

8. The method according to claim 7, wherein when a flag is set in a particular test result area of one memory zone, a flag is cleared in a corresponding test result area of another memory zone.

9. The method according to claim 7, wherein the number of sorting receptacles corresponds to the number of memory zones.

10. The method according to claim 9, wherein the step of arranging for substantially simultaneous placement of each electronic element belonging in a first sorting receptacle into the first sorting receptacle further comprises:

identifying a particular memory zone corresponding to the first sorting receptacle;

for each test result area of the identified memory zone, determining whether the flag in each test result area indicates an electronic element associated with the test result area belongs in the first sorting receptacle; and

arranging for substantially simultaneous placement of each electronic element in the first sorting receptacle when the flags in the test result areas associated with the electronic elements indicate that the electronic elements belong in the first sorting receptacle.

11. A computer-readable medium encoded with a computer program which, when loaded into a processor, implements the method of claim 4.