Method and system for device characterization with array and decoder

• US 20080136437A1
• Filed: 01/23/2008
• Published: 06/12/2008
• Est. Priority Date: 12/22/2005
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: Bin, Gong
• Granted Patent: US 7,521,955 B2
• Time in Patent Office: Days
• US Class Current: 324/763
• CPC Class Codes: G01R 31/275 for testing individual semiconductor components within integrated circuits
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence

Abstract

A system and method for testing devices. The system includes a plurality of pads and a decoder coupled to a plurality of devices. The decoder is configured to receive a plurality of selection signals from the plurality of pads and select a device from the plurality of devices based on at least information associated with the plurality of selection signals. Additionally, the system includes one or more pads connected to the selected device. At least one of the one or more pads is not connected to any of the plurality of devices other than the selected device. The one or more pads are used for testing the selected device.

Claims

1-5. -5. (canceled)

6. A system for testing transistors, the system comprising:

a plurality of pads;

a plurality of transistors including a first transistor, the first transistor including a first terminal, a second terminal, a third terminal, and a fourth terminal;

a decoder coupled to the plurality of transistors and configured to receive a plurality of selection signals from the plurality of pads and select the first transistor from the plurality of transistors based on at least information associated with the plurality of selection signals, the decoder being adapted to generate a control signal based at least on the selection signals;

a first pad coupled to the first terminal of the first transistor through a second transistor, the first terminal of the first transistor being either a source terminal or a drain terminal of the first transistor, the second transistor including a fourth, a fifth, and a sixth terminal, the sixth terminal being configured to receive the control signal from the decoder, the first pad being electrically coupled to at most one of the plurality of the transistors including the first transistor;

a second pad coupled to the second terminal of the first transistor through a third transistor, the third transistor comprising a seventh terminal, a eighth terminal, and a ninth terminal, the second terminal of the second transistor being a gate terminal of the first transistor, the second pad being electrically connected to at most one of the plurality of the transistors including the first transistor;

a third pad electrically connected to the third terminal of the first transistor, the third terminal being a substrate terminal of the first transistor; and

a fourth pad electrically connected to the fourth terminal of the first transistor, the fourth terminal being the source terminal of the first transistor if the first terminal is the drain terminal of the first transistor, or the drain terminal of the first transistor if the first terminal is the source terminal of the first transistor.

7. The system of claim 6 wherein:

the sixth terminal is a gate terminal of the second transistor;

the ninth terminal is a gate terminal of the third transistor;

the fourth terminal and the fifth terminal of the second transistor are either a source terminal or a drain terminal of the second transistor, the fourth terminal being the drain terminal of the second transistor if the fifth terminal is the source terminal of the second transistor and the fourth terminal being the source terminal of the second transistor if the fifth terminal is the drain terminal of the second transistor; and

the seventh terminal and the eighth terminal of the third transistor are either a source terminal or drain terminal of the third transistor, the seventh terminal being the drain terminal of the third transistor if the eighth terminal is the source terminal of the third transistor and the seventh terminal being the source terminal of the third transistor if the eighth terminal is the drain terminal of the third transistor.

8. The system of claim 6 wherein:

the first pad is coupled to the first terminal of the first transistor further through an electrical connection between the first pad and the fourth terminal of the second transistor and an electrical connection between the fifth terminal of the second transistor and the first terminal of the first transistor; and

the second pad is coupled to the second terminal of the first transistor further through an electrical connection between the second pad and the seventh terminal of the third transistor and an electrical connection between the eighth terminal of the third transistor and the second terminal of the first transistor.

9. The system of claim 7 wherein the sixth terminal of the second transistor and the ninth terminal of the third transistor are electrically connected, and the ninth terminal of the third transistor is adapted to receive the control signal from the decoder to select the first transistor for testing.

10. The system of claim 6 is further adapted for testing transistors wherein the plurality of transistors is arranged in an array.

11. The system of claim 6 wherein the plurality of selection signals includes an N number of signals, the control signal being capable of selecting the first transistor from up to 2 number of transistors.

12. The system of claim 11 wherein N is 8 and the plurality of transistors consists of 256 transistors.

13. The system of claim 6 wherein the plurality of transistors and MOS transistors.

14. The system of claim 6 wherein the control signal selects one transistor at a time for testing.