Method and system for device characterization with array and decoder
0 Assignments
0 Petitions
Accused Products
Abstract
A system and method for testing devices. The system includes a plurality of pads and a decoder coupled to a plurality of devices. The decoder is configured to receive a plurality of selection signals from the plurality of pads and select a device from the plurality of devices based on at least information associated with the plurality of selection signals. Additionally, the system includes one or more pads connected to the selected device. At least one of the one or more pads is not connected to any of the plurality of devices other than the selected device. The one or more pads are used for testing the selected device.
-
Citations
14 Claims
-
1-5. -5. (canceled)
-
6. A system for testing transistors, the system comprising:
-
a plurality of pads; a plurality of transistors including a first transistor, the first transistor including a first terminal, a second terminal, a third terminal, and a fourth terminal; a decoder coupled to the plurality of transistors and configured to receive a plurality of selection signals from the plurality of pads and select the first transistor from the plurality of transistors based on at least information associated with the plurality of selection signals, the decoder being adapted to generate a control signal based at least on the selection signals; a first pad coupled to the first terminal of the first transistor through a second transistor, the first terminal of the first transistor being either a source terminal or a drain terminal of the first transistor, the second transistor including a fourth, a fifth, and a sixth terminal, the sixth terminal being configured to receive the control signal from the decoder, the first pad being electrically coupled to at most one of the plurality of the transistors including the first transistor; a second pad coupled to the second terminal of the first transistor through a third transistor, the third transistor comprising a seventh terminal, a eighth terminal, and a ninth terminal, the second terminal of the second transistor being a gate terminal of the first transistor, the second pad being electrically connected to at most one of the plurality of the transistors including the first transistor; a third pad electrically connected to the third terminal of the first transistor, the third terminal being a substrate terminal of the first transistor; and a fourth pad electrically connected to the fourth terminal of the first transistor, the fourth terminal being the source terminal of the first transistor if the first terminal is the drain terminal of the first transistor, or the drain terminal of the first transistor if the first terminal is the source terminal of the first transistor. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14)
-
Specification