Input Termination For Delay Locked Loop Feedback With Impedance Matching

• US 20080136443A1
• Filed: 12/07/2006
• Published: 06/12/2008
• Est. Priority Date: 12/07/2006
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Wong, Tak Kwong
• Granted Patent: US 7,898,288 B2
• Time in Patent Office: Days
• US Class Current: 326/30
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used

Abstract

A reference output circuit for generating an output clock signal for driving signals off of an integrated circuit chip uses a switched terminated load in combination with an output buffer to generate a feedback clock signal, which is used, in combination with a reference input clock signal, to generate the output clock signal. The switched terminated load uses transistors having the same size as transistors in the output buffer. The switched terminated load draws the same DC current as the output buffer. As a result, the switched terminated load and the output buffer have the same electro-migration performance. Pull-up and pull-down MOS impedances of the switched terminated load are easily adjusted during switching periods of the switched terminated load. The design of the switched terminated load minimizes variations in the terminated load impedance due to MOS impedance variations.

Claims

1. A reference output circuit comprising:

a control circuit configured to provide an output clock signal for driving one or more output signals; and

a terminated load module configured to switch between a pull-up configuration and a pull-down configuration in response to the output clock signal, wherein the terminated load module emulates terminated loads driven by the output signals.

2. The reference output circuit of claim 1, wherein the control circuit comprises circuitry for generating the output clock signal in response to a feedback clock signal and in input clock signal.

3. The reference output circuit of claim 2, wherein the control circuit comprises:

a first comparator coupled to receive the feedback clock signal and a reference voltage signal associated with a cross-over voltage of the feedback clock signal and the input clock signal;

a second comparator coupled to receive the input clock signal and the reference voltage signal; and

a delay locked loop circuit coupled to receive output signals from the first and second comparators, and in response, provide the output clock signal.

4. The reference output circuit of claim 2, further comprising an output buffer circuit configured to drive the feedback clock signal in response to the output clock signal, wherein the output buffer circuit is configured to switch between a pull-up configuration and a pull-down configuration.

5. The reference output circuit of claim 4, wherein the output buffer circuit includes a pull-up transistor and a pull-down transistor, and the terminated load module includes a pull-up transistor and a pull-down transistor, wherein the pull-up transistor of the output buffer circuit is the same size as the pull-up transistor of the terminated load module, and the pull-down transistor of the output buffer circuit is the same size as the pull-down transistor of the terminated load module.

6. The reference output circuit of claim 4, wherein the output buffer circuit includes a pull-up transistor and a pull-down transistor, and the terminated load module includes a pull-up transistor and a pull-down transistor, wherein the pull-up transistor of the output buffer circuit has the same on-resistance as the pull-up transistor of the terminated load module, and the pull-down transistor of the output buffer circuit has the same on-resistance as the pull-down transistor of the terminated load module.

7. The reference output circuit of claim 4, wherein the output buffer circuit includes a pull-up transistor and a pull-down transistor, and the terminated load module includes a pull-up transistor and a pull-down transistor, wherein the pull-up transistor of the output buffer circuit, the pull-up transistor of the terminated load module, the pull-down transistor of the output buffer circuit and the pull-down transistor of the terminated load module all have approximately the same on-resistance.

8. The reference output circuit of claim 4, further comprising a feedback path configured to receive the feedback clock signal from the output buffer circuit, wherein the feedback path includes a capacitor and the terminated load module.

9. The reference output circuit of claim 8, wherein the output buffer circuit includes a pull-up transistor and a pull-down transistor, which are commonly coupled to a signal line of the feedback path through a first resistor, and the terminated load module includes a pull-up transistor coupled to the signal line through a second resistor, and a pull-down transistor coupled to the signal line through a third resistor, wherein the second and third resistors each have a resistance which is greater than a resistance of the first resistor.

10. The reference output circuit of claim 9, wherein the second and third resistors each have a resistance three times greater than the resistance of the first resistor.

11. The reference output circuit of claim 8, wherein the output buffer circuit includes a pull-up transistor and a pull-down transistor, which are commonly coupled to a signal line of the feedback path through a first resistor, and the terminated load module includes a pull-up transistor and a pull-down transistor, which are commonly coupled to the signal line of the feedback path through a second resistor, wherein the second resistor has a resistance greater than a resistance of the first resistor.

12. The reference output circuit of claim 11, wherein the resistance of the second resistor is about three times greater than the resistance of the first resistor.

13. The reference output circuit of claim 1, further comprising a delay circuit configured to provide a delayed output clock signal in response to the output clock signal, wherein the terminated load module is configured to switch between the pull-up configuration and the pull-down configuration in response to the delayed output clock signal.

14. A method for driving signals off of an integrated circuit chip, the method comprising:

generating an output clock signal;

driving one or more signals off of the integrated circuit chip to one or more corresponding terminated loads in response to the output clock signal;

switching a terminated load circuit on the integrated circuit chip in response to the output clock signal, wherein the terminated load circuit emulates the terminated loads located off of the integrated circuit chip.

15. The method of claim 14, further comprising:

driving a feedback clock signal to a first logic state in response to a first transition of the output clock signal, wherein the feedback clock signal is driven to the first logic state by;

turning on a pull-up transistor in an output buffer circuit;

turning on a pull-up transistor in the terminated load circuit;

turning off a pull-down transistor in the output buffer circuit;

turning off a pull-down transistor in the terminated load circuit; and

then

turning off the pull-up transistor in the terminated load circuit and turning on the pull-down transistor in the terminated load circuit after the feedback clock signal has been driven to the first logic state.

16. The method of claim 15, further comprising:

driving the feedback clock signal to a second logic state in response to a second transition of the output clock signal, wherein the feedback clock signal is driven to the second logic state by;

turning on the pull-down transistor in the output buffer circuit;

maintaining the pull-down transistor in the terminated load circuit in a turned on condition;

turning off the pull-up transistor in the output buffer circuit;

maintaining the pull-up transistor in the terminated load circuit in a turned off condition; and

then

turning off the pull-down transistor in the terminated load circuit and turning on the pull-up transistor in the terminated load circuit after the feedback clock signal has been driven to the second logic state.

17. The method of claim 16, further comprising adjusting an on-resistance of the pull-up transistor of the terminated load circuit when the pull-up transistor of the terminated load module is turned off.

18. The method of claim 17, further comprising adjusting an on-resistance of the pull-down transistor of the terminated load circuit when the pull-down transistor of the terminated load module is turned off.