LOW-VOLTAGE BAND-GAP REFERENCE VOLTAGE BIAS CIRCUIT

• US 20080136504A1
• Filed: 11/27/2007
• Published: 06/12/2008
• Est. Priority Date: 12/07/2006
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: PARK, Seong Soo, KIM, Young Ho
• Granted Patent: US 7,808,305 B2
• Time in Patent Office: Days
• US Class Current: 327/539
• CPC Class Codes: G05F 3/30 Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities G05F3/26 takes precedence

Abstract

A low-voltage band-gap reference voltage bias circuit according to the present invention can provide a stable reference voltage at a supply voltage of about 1V or lower irrespective of a power supply voltage or temperature variation by flowing a PTAT mirror current into diodes and resistors and obtaining the average of voltages at two nodes. Furthermore, the low-voltage band-gap reference voltage bias circuit has simple configuration, reduces the resistance of a resistor that occupies a large chip area, uses small-sized diodes, and thus increases the integration density of the band-gap reference voltage bias circuit.

Claims

1. A low-voltage band-gap reference voltage bias circuit comprising:

first and second PMOS transistors having gate terminals commonly coupled to a first node, source terminals commonly coupled to a power supply terminal, and drain terminals respectively coupled to second and third nodes, and constituting a current mirror circuit;

third and fourth PMOS transistors having gate terminals commonly coupled to the first node, source terminals commonly coupled to the power supply terminal, and drain terminals respectively coupled to fourth and fifth nodes;

a feedback amplifier having a non-inverting input terminal and an inverting input terminal respectively coupled to the second and third nodes and an output terminal coupled to the first node;

a first resistor coupled between the third node and a sixth node;

a second resistor coupled between the fifth node and a ground terminal;

first through third bipolar transistors having emitters respectively coupled to the second, sixth, and fourth nodes and collectors and bases that are grounded; and

first and second elements coupled in series between the fourth and fifth nodes, and having high impedances to cut off the flow of current to obtain an average of voltages at the fourth and fifth nodes,

wherein the average of the voltages at the fourth and fifth nodes is used as a reference voltage.

3. The circuit according to claim 1, wherein each of the first and second elements is a diode.

2. A low-voltage band-gap reference voltage bias circuit comprising:

first and second PMOS transistors having gate terminals commonly coupled to a first node, source terminals commonly coupled to a power supply terminal, and drain terminals respectively coupled to second and third nodes, and constituting a current mirror circuit;

third and fourth PMOS transistors having gate terminals commonly coupled to the first node, source terminals commonly coupled to the power supply terminal, and drain terminals respectively coupled to fourth and fifth nodes;

a feedback amplifier having a non-inverting input terminal and an inverting input terminal respectively coupled to the second and third nodes and an output terminal coupled to the first node;

a first resistor coupled between the third node and a sixth node;

a second resistor coupled between the fourth node and a ground terminal;

a first diode coupled between the second node and the ground terminal;

a second diode coupled between the sixth node and the ground terminal;

a third diode coupled between the fifth node and the ground terminal; and

first and second elements coupled in series between the fourth and fifth nodes, and having high impedances to cut off the flow of current to obtain an average of voltages at the fourth and fifth nodes,

wherein the average of the voltages at the fourth and fifth nodes is used as a reference voltage.

4. The circuit according to claim 2, wherein each of the first and second elements is a diode.