PHASE LOCKED LOOP WITH ADAPTIVE PHASE ERROR COMPENSATION

• US 20080136532A1
• Filed: 12/07/2006
• Published: 06/12/2008
• Est. Priority Date: 12/07/2006
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Naviasky, Eric, HUFFORD, Michael M., Caviglia, Tony
• Granted Patent: US 7,579,886 B2
• Time in Patent Office: Days
• US Class Current: 331/10
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

An adaptive phase-locked loop (PLL) circuit produces an output signal having a frequency in reference to the frequency of a reference signal. The PLL circuit includes an oscillator configured to generate the output signal according to a frequency control signal, and a processing circuit configured to generate a feedback signal deriving from the output signal. An adjustable shift circuit is provided to time-shift the feedback signal. The PLL further includes a phase comparison circuit configured to generate a phase error signal indicating a phase error between the time-shifted feedback signal and the reference signal, and a control circuit configured to generate the frequency control signal based on the phase error signal. The adjustable shift circuit adjusts a time-shift amount to time-shift the feedback signal according to the phase error signal.

Claims

1. An adaptive phase-locked loop (PLL) circuit for producing an output signal having a frequency in reference to the frequency of a reference signal, the PLL circuit comprising:

an oscillator configured to generate the output signal according to a frequency control signal;

a processing circuit configured to generate a feedback signal deriving from the output signal;

an adjustable shift circuit configured to time-shift the feedback signal;

a phase comparison circuit configured to generate a phase error signal indicating a phase error between the time-shifted feedback signal and the reference signal; and

a control circuit configured to generate the frequency control signal based on the phase error signal;

wherein the adjustable shift circuit adjusts a time-shift amount to time-shift the feedback signal according to the phase error signal.

2. The PLL circuit of claim 1, wherein the processing circuit comprises a frequency divider.

3. The PLL circuit of claim 2, wherein the processing circuit comprises a M/M+1 divider.

4. The PLL circuit of claim 1, wherein the adjustable shift circuit operates to delay and advance the feedback signal relative to a reference clock signal.

5. The PLL circuit of claim 1, wherein the time-shift amount is determined based on a condition of the phase error occurring in a previous cycle.

6. The PLL circuit of claim 1 further including a mismatch compensation circuit configured to modify the phase error signal by time-shifting the phase error signal to compensate for a mismatch condition occurring in the PLL circuit, and to provide the modified phase error signal to the adjustable shift circuit for adjusting the time-shift amount to time-shift the feedback signal.

7. The PLL circuit of claim 6, wherein the mismatch compensation circuit and the adjustable shift circuit perform time-shifting functions at different times.

8. The PLL circuit of claim 6, wherein the phase error signal includes an up signal and a down signal, and at least one of the up signal and the down signal is time-shifted according to an arrival sequence of the up signal and the down signal.

9. An adaptive method for controlling a phase-locked loop (PLL) circuit to produce an output signal having a frequency in reference to the frequency of a reference signal, the method comprising:

generating the output signal according to a frequency control signal;

generating a feedback signal deriving from the output signal;

time-shifting the feedback signal;

generating a phase error signal indicating a phase error between the time-shifted feedback signal and the reference signal; and

generating the frequency control signal based on the phase error;

wherein a time-shift amount to the feedback signal is varied according to a condition of the phase error.

10. The method of claim 9, wherein the feedback signal is generated by dividing the frequency of the output signal.

11. The method of claim 10, wherein the frequency of the output signal is selectively divided by M and M+1.

12. The method of claim 9, wherein time-shifting further comprises delaying and advancing the feedback signal relative to a reference clock signal.

13. The method of claim 9, wherein the time-shift amount is adjusted based on a condition of the phase error occurring in a previous cycle.

14. The method of claim 9 further including:

modifying the phase error signal by time-shifting the phase error signal to compensate for a mismatch condition occurring in the PLL circuit, and

providing the modified phase error signal for adjusting the time-shift amount to time-shift the feedback signal.

15. The method of claim 14, wherein modifying the phase error signal and time-shifting the feedback signal are performed at different reference clocks.

16. The method of claim 14, wherein the phase error signal includes an up signal and a down signal, and at least one of the up signal and the down signal is time-shifted according to an arrival sequence of the up signal and the down signal.

17. An adaptive phase-locked loop (PLL) circuit for producing an output signal having a frequency in reference to the frequency of a reference signal, the PLL circuit comprising:

means for generating the output signal according to a frequency control signal;

means for generating a feedback signal deriving from the output signal;

adjustable means for time-shifting the feedback signal;

means for generating a phase error signal indicating a phase error between the time-shifted feedback signal and the reference signal; and

means for generating the frequency control signal based on the phase error signal;

wherein the adjustable means adjusts a time-shift amount to time-shift the feedback signal according to the phase error signal.

18. The PLL circuit of claim 17, wherein the time-shift amount is adjusted based on a condition of the phase error occurring in a previous cycle.

19. The PLL circuit of claim 17 further including mismatch compensation means for modifying the phase error signal by time-shifting the phase error signal to compensate for a mismatch condition occurring in the PLL circuit, and for providing the modified phase error signal to the adjustable means for adjusting the time-shift amount to time-shift the feedback signal.

20. The PLL circuit of claim 19, wherein the phase error signal includes an up signal and a down signal, and at least one of the up signal and the down signal is time-shifted according to an arrival sequence of the up signal and the down signal.