METHOD AND SYSTEM FOR FAST PLL CLOSE-LOOP SETTLING AFTER OPEN-LOOP VCO CALIBRATION

• US 20080136533A1
• Filed: 12/29/2006
• Published: 06/12/2008
• Est. Priority Date: 12/06/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Li, Dandan
• Granted Patent: US 7,616,069 B2
• Time in Patent Office: Days
• US Class Current: 331/16
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

Aspects of a method and system for a fast phase-locked loop (PLL) close-loop settling after an open-loop voltage controlled oscillator (VCO) calibration are provided. A fractional-N PLL synthesizer may comprise a VCO, a phase-frequency detector (PFD), a D flip-flop, a divider, a charge pump, and a loop filter. The synthesizer may disable the PFD based on a control signal indicating the start of VCO open-loop calibration. After open-loop calibration, the synthesizer may subsequently enable a PLL closed-loop settling and may enable the PFD to control the charge pump when the input reference signal phase lags a phase of a divider signal generated by the divider. The D flip-flop may enable and disable the PFD. During open-loop calibration, the loop filter may be discharged via a leakage current in the charge pump. During closed-loop settling, the loop filter may be charged by the charge pump via control of the PFD.

Claims

1. A method for signal processing, the method comprising:

in a fractional-N phase-locked-loop (PLL) synthesizer comprising a phase-frequency detector (PFD) and a VCO, disabling of said PFD via a control signal generated based on a received signal that indicates enabling an open-loop calibration of said VCO; and

subsequently enabling said PFD via said control signal when said received signal indicates enabling a closed-loop settling of said PLL and when a phase of an input reference signal lags a phase of a divider signal generated by a divider in said fractional-N PLL synthesizer.

2. The method according to claim 1, comprising generating said control signal in a D flip-flop in said fractional-N PLL synthesizer.

3. The method according to claim 1, wherein said PFD controls a charge pump in said fractional-N PLL synthesizer via a single control signal.

4. The method according to claim 3, comprising discharging a loop filter in said fractional-N PLL synthesizer via a constant leakage current in said charge pump during said open-loop calibration.

5. The method according to claim 3, comprising charging a loop filter in said fractional-N PLL synthesizer via a charge up portion in said charge pump during said closed-loop settling.

6. The method according to claim 3, wherein said charge pump is programmable.

7. The method according to claim 1, wherein said divider is a multi-modulus divider (MMD).

8. The method according to claim 1, comprising configuring a conversion factor in said VCO.

9. The method according to claim 1, comprising disconnecting said VCO from a loop filter in said fractional-N PLL synthesizer during said open-loop calibration.

10. The method according to claim 1, comprising connecting said VCO to a loop filter in said fractional-N PLL synthesizer during said closed-loop settling.

11. A system for signal processing, the system comprising:

a fractional-N phase-locked-loop (PLL) synthesizer that comprises a phase-frequency detector (PFD) and a VCO;

said fractional-N PLL synthesizer enables the disabling of said PFD via a control signal generated based on a received signal that indicates enabling an open-loop calibration of said VCO; and

said fractional-N PLL synthesizer subsequently enables the enabling of said PFD via said control signal when said received signal indicates enabling a closed-loop settling of said PLL and when a phase of an input reference signal lags a phase of a divider signal generated by a divider in said fractional-N PLL synthesizer.

12. The system according to claim 11, wherein said fractional-N PLL synthesizer comprises a D flip-flop that enables generation of said control signal.

13. The system according to claim 11, wherein said PFD controls a charge pump in said fractional-N PLL synthesizer via a single control signal.

14. The system according to claim 13, wherein said fractional-N PLL synthesizer enables discharging a loop filter in said fractional-N PLL synthesizer via a constant leakage current in said charge pump during said open-loop calibration.

15. The system according to claim 13, wherein said fractional-N PLL synthesizer enables charging a loop filter in said fractional-N PLL synthesizer via a charge up portion in said charge pump during said closed-loop settling.

16. The system according to claim 13, wherein said charge pump is programmable.

17. The system according to claim 15, wherein said divider is a multi-modulus divider (MMD).

18. The system according to claim 11, wherein said fractional-N PLL synthesizer enables configuration of a conversion factor in said VCO.

19. The system according to claim 11, wherein said fractional-N PLL synthesizer enables disconnection of said VCO from a loop filter in said fractional-N PLL synthesizer during said open-loop calibration.

20. The system according to claim 11, wherein said fractional-N PLL synthesizer enables connection of said VCO to a loop filter in said fractional-N PLL synthesizer during said closed-loop settling.