NOVEL MATCH MISMATCH EMULATION SCHEME FOR AN ADDRESSED LOCATION IN A CAM

• US 20080137388A1
• Filed: 12/08/2006
• Published: 06/12/2008
• Est. Priority Date: 12/08/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Kuliyampattil, Nisha Padattil, Sheffield, Bryan D., Krishnan, Rengarajan S., Sachan, Rashmi
• Granted Patent: US 7,471,536 B2
• Time in Patent Office: Days
• US Class Current: 365/49.16
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

A novel match/mismatch emulation scheme for an addressed location in a CAM system that includes a plurality of CAM blocks. The plurality of CAM blocks are organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of CAM cells and associated read/write bit lines connecting the group of CAM cells to an addressed search circuit. During debug mode, where the individual array cells do not participate in search, all the cells in the debug column behave the same way to emulate a match/mismatch on all words. The circuit provides a control input to include address evaluation of a debug cell in a row. The circuit also provides simultaneous switching noise analysis on an evaluating row. The resulting CAM cell provides a circuit to test individual rows for defects and noise analysis.

Claims

1. A content addressable memory (CAM) system comprising:

a write/search bitline decoder and driver circuit; and

a CAM cell array including multiple CAM cells, wherein the CAM cell array is organized into at least one rectangular array having rows each having a plurality of CAM cells, wherein each CAM cell is associated with a row and a column of the CAM cell array, wherein each CAM cell is associated with a row and a column in the CAM block, and wherein each CAM cell comprising;

an associated read/write bit line coupled between each CAM cell and the write/search bitline decoder and driver circuit and wherein during a write cycle the write bit line decoder and driver circuit to write a data bit to each CAM cell via the associated read/write bit line; and

an associated addressed search circuit wherein during a debug mode, the search circuit allows the CAM to emulate a single row match/mismatch.

2. The system of claim 1, further comprising:

a sense amplifier; and

a pair of precharge circuits, wherein each CAM cell is coupled to the sense amplifier and the pair of precharge circuits via the associated read/write bit line, wherein during a read cycle the sense amplifier to read a stored data bit in each CAM cell via the associated read/write bit line, and wherein during a precharge cycle the pair of precharge circuits to charge each read/write bit line substantially after completing the read cycle.

3. The system of claim 2, further comprising:

an input/output (I/O) driver; and

an associated read/write complement bit line coupled between each CAM cell in each CAM block and the write/search bitline decoder and driver circuit, wherein during a read cycle the I/O driver to read a stored data bit and a stored complement data bit in each CAM cell via the associated read/write complement bit line and during a write cycle the I/O driver to write a data bit to each CAM cell via the associated read/write complement bit line, wherein during the precharge cycle the write/search bitline decoder and driver circuit to precharge each associated read/write complement bit line substantially after completing the write cycle, and wherein the pair of precharge circuits to precharge the read/write bit lines substantially after completing the read/write cycle.

4. The system of claim 3, further comprising:

a search bit line and a search bit complement line that are connected between each CAM cell and the write/search bitline decoder and driver circuit, and during a precharge cycle the write/search bitline decoder and driver circuit to drive each search bit line and search bit complement line.

5. The system of claim 4, wherein each CAM cell further comprises:

a pair of memory elements for storing a data bit and a complement data bit; and

a pair of comparison circuits coupled to the pair of memory elements that compares the stored data bit and the stored data bit complement with a received compare data bit via the search bit line and the search complement bit line, respectively, and drives a match/mismatch signal onto an associated match line ML when the stored data bit and the stored complement data bit are not equal to the compare data bit.

6. The system of claim 5, wherein the pair of memory elements is a pair of SRAM cells and wherein the addressed search circuit comprises a first pair of N channel transistors, wherein the gates of the N channel transistors are coupled to a search bit line SBIT and a control bit line CNTL respectively, a second pair of N channel transistors coupled to a word line and the match line ML, wherein the control line CNTL is coupled to the match line ML, and wherein during the debug mode the addressed search circuit receives the internal signals CNTL and SBIT and performs the operation to indicate whether there is a match/mismatch on addressed row.

7. The system of claim 4, wherein the write/search bitline decoder and driver circuit comprises:

a data decode circuit for receiving input signals from the I/O driver during normal mode;

a search bitline disable circuit to bypass decoding the input signals from the I/O driver during debug mode and keep search bitlines in its previous predischarged state; and

a write bit line driver circuit associated with each read/write bit line and each complement read/write line of a CAM cell coupled between the data decode circuit and the associated read/write bit line and the complement read/write line.

8. The system of claim 7, wherein the search bitline disable circuit of each write bit line driver circuit comprises:

a first inverter wherein the input signal is DEBUG and an output; and

a NAND gate including a first input, second input and an output, wherein the first input of the first NAND gate is coupled to receive a SEARCH-ENABLE signal, and wherein the second input is coupled to receive the output of the first inverter, wherein the output of the NAND gate is the input to a second inverter, wherein the output from the second inverter is coupled to a search bit line generation block, and wherein the output of the search bit line generational block is the search bit line.

9. A ternary content addressable memory (TCAM) circuit comprising:

a write/search bitline decoder and driver circuit; and

a CAM cell array including (MXN) CAM cells arranged in M number of rows and N number of columns, wherein each CAM block comprising;

(m×

n) CAM cells arranged in a rectangular array of m number of rows and n number columns;

an associated read/write bit line coupled between each CAM cell in each CAM block and the write/search bitline decoder and driver circuit, and wherein during a write cycle the write/search bitline decoder and driver circuit to write a data bit to each CAM cell via the associated read/write bit line; and

an associated addressed search circuit wherein during a debug mode, and wherein the search circuit allows the CAM to emulate a single row match/mismatch.

10. The circuit of claim 9, further comprising:

a sense amplifier; and

a pair of precharge circuits, wherein each CAM cell is coupled to the sense amplifier and the pair of precharge circuits via the associated read/write bit line, wherein during a read cycle the sense amplifier to read a stored data bit in each CAM cell via the associated read/write bit line, and wherein during a precharge cycle the pair of precharge circuits to charge each read/write bit line substantially after completing the read cycle.

11. The circuit of claim 10, further comprising:

an input/output (I/O) driver; and

an associated read/write complement bit line coupled between each CAM cell in each CAM block and the write/search bitline decoder and driver circuit, wherein during a read cycle the I/O driver to read a stored data bit and a stored complement data bit in each CAM cell via the associated read/write complement bit line and during a write cycle the I/O driver to write a data bit to each CAM cell via the associated read/write complement bit line, and wherein during the precharge cycle the write bit line driver circuit to precharge each associated read/write complement bit line substantially after completing the search cycle and the write cycle.

12. The system of claim 9, wherein the write/search bitline decoder and driver circuit comprises:

a data decode circuit for receiving input signals from the I/O driver during normal mode;

a search bitline disable circuit to bypass decoding the input signals from the I/O driver during debug mode and keep search bitlines in its previous predischarged state; and

a write bit line driver circuit associated with each read/write bit line and each complement read/write line of a CAM cell coupled between the data decode circuit and the associated read/write bit line and the complement read/write line.

13. The system of claim 12, wherein the search bitline disable circuit of each write bit line driver circuit comprises:

a first inverter including an input signal DEBUG and an output; and

a NAND gate including a first input, a second input and an output, wherein the first input of the NAND gate is coupled to receive a SEARCH-ENABLE signal, and wherein the second input is coupled to receive the output of the first inverter, wherein the output of the NAND gate is the input to a second inverter, wherein the output from the second inverter is coupled to a search bit line generation block, and wherein the output of the search bit line generational block is the search bit line.

14. A method of bypassing the decoding in a CAM block array, wherein the CAM block array includes a plurality of CAM blocks, wherein the CAM block array is organized into at least one rectangular array having rows each having a plurality of CAM blocks, wherein each CAM block including a group of CAM cells, wherein each CAM cell is coupled to a read/write bit line and a search bit line comprising the steps of:

reading a CAM cell using an associated read/write bit line;

precharging each read/write bit line substantially after completing a read cycle using one or more precharge circuits;

writing to the CAM cell using an associated read/write bit line;

precharging each read/write bit line substantially after completing a write cycle using a precharge circuit;

precharging each search bit line in the CAM block array using the precharge circuit substantially after completing a search operation; and

determining if the CAM cell is used in a normal mode or a debug mode, and allowing the CAM to emulate a single row match/mismatch during a debug mode.