Single Chip Having Magnetoresistive Memory

• US 20080137399A1
• Filed: 01/25/2005
• Published: 06/12/2008
• Est. Priority Date: 01/25/2005
• Status: Abandoned Application

• Current Assignee: Northern Lights Semiconductor Corp.
• Original Assignee: Northern Lights Semiconductor Corp.
• Inventors: Chan, Chien-Chiang, Lai, James Chyi
• Application Number:
  US11/814,524
• Publication Number:
  US 20080137399A1
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207

Abstract

A single chip has a substrate and at least one magnetoresistive memory layer. The substrate has an underlying memory and a control circuit. The magnetoresistive memory layer is placed on the substrate, and has a plurality of magnetoresistive random access memory cells controlled by the control circuit.

Claims

1. A single chip having a magnetoresistive memory, comprising:

a substrate comprising an underlying memory and a control circuit; and

at least one magnetoresistive memory layer on the substrate, wherein the magnetoresistive memory layer comprises a plurality of magnetoresistive random access memory cells controlled by the control circuit.

2. The single chip of claim 1, wherein the underlying memory is a volatile or non-volatile memory.

3. The single chip of claim 2, wherein the volatile memory is DRAM or SRAM.

4. The single chip of claim 2, wherein the non-volatile memory is EPROM, EEPROM, FLASH or FeRAM.

5. The single chip of claim 1, wherein the substrate further comprises a microprocessor, a RFID circuit or an ASIC circuitry.

6. The single chip of claim 5, wherein the control circuit comprises a plurality of electronic elements, and some of the electronic elements are embedded in the microprocessor, a RFID circuit or an ASIC circuitry.

7. The single chip of claim 1, wherein the control circuit comprises a plurality of electronic elements.

8. The signal chip of claim 7, wherein some of the electronic elements are positioned within a region of the substrate.

9. The single chip of claim 1, wherein the magnetoresistive memory layer comprises multiple stacked layers.

10. The signal chip of claim 1, wherein the substrate is silicon or GaAs.

11. A single chip having magnetoresistive memory, comprising:

a substrate comprising a plurality of logic circuits and a control circuit; and

at least one magnetoresistive memory layer on the substrate, wherein the magnetoresistive memory layer comprises a plurality of magnetoresistive random access memory cells controlled by the control circuit.

12. The single chip of claim 11, wherein the substrate further comprises a volatile or non-volatile memory.

13. The single chip of claim 12, wherein the volatile is DRAM or SRAM.

14. The single chip of claim 12, wherein the non-volatile is EPROM, EEPROM, FLASH or FeRAM.

15. The single chip of claim 11, wherein the logic circuits comprise a microprocessor, a RFID circuit or an ASIC circuitry.

16. The single chip of claim 11, wherein the control circuit comprises a plurality of electronic elements.

17. The signal chip of claim 16, wherein some of the electronic elements are embedded in the logic circuits.

18. The signal chip of claim 16, wherein some of the electronic elements are positioned within a region of the substrate.

19. The single chip of claim 11, wherein the magnetoresistive memory layer comprises multiple stacked layers.

20. The signal chip of claim 11, wherein the substrate is silicon or GaAs.