Multi-level cell memory device and method thereof

• US 20080137414A1
• Filed: 06/07/2007
• Published: 06/12/2008
• Est. Priority Date: 12/06/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Dong Ku, Park, Sung Chung, Kong, Jun Jin, Lee, Young Hwan
• Granted Patent: US 7,962,831 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A Multi-Level Cell (MLC) memory device and method thereof are provided. The example MLC memory device may be configured to perform data operations, and may include an MLC memory cell, a first coding device performing a first coding function, the first coding function being one of an encoding function and a decoding function, a second coding device performing a second coding function, the second coding function being one of an encoding function and a decoding function and a signal module configured to perform at least one of instructing the MLC memory cell to store data output by the second coding device if the first and second coding functions are encoding functions, and generating a demapped bit stream based on data retrieved from the MLC memory cell if the first and second coding functions are decoding functions.

Claims

1. A Multi-Level Cell (MLC) memory device configured to perform data operations, comprising:

an MLC memory cell;

a first coding device performing a first coding function, the first coding function being one of an encoding function and a decoding function;

a second coding device performing a second coding function, the second coding function being one of an encoding function and a decoding function; and

a signal module configured to perform at least one of instructing the MLC memory cell to store data output by the second coding device if the first and second coding functions are encoding functions, and generating a demapped bit stream based on data retrieved from the MLC memory cell if the first and second coding functions are decoding functions.

2. The MLC memory device of claim 1, wherein

the first coding function is a first encoding function and the second coding function is a second encoding function,

the first coding device is an outer encoder encoding data based on the first encoding function to generate an outer encoded bit stream,

the second coding device is an inner encoder encoding the outer encoded bit stream based on the second encoding function to generate an inner encoded bit stream, and

the signal module is a signal mapping module instructs the MLC memory cell to store the inner encoded bit stream as the stored data in the MLC memory cell.

3. The MLC memory device of claim 2, wherein the MLC memory cell corresponds to an m-bit MLC memory cell with m being a positive integer, and the signal mapping module instructing the MLC memory cell via a program pulse corresponding to any one of 2^m number of voltage distributions generated by a 2^m pulse amplitude modulation (PAM).

4. The MLC memory device of claim 2, wherein the first encoding scheme includes linear block encoding.

5. The MLC memory device of claim 2, wherein the second encoding scheme includes convolutional code encoding.

6. The MLC memory device of claim 2, wherein the inner encoder includes:

a mother code encoder encoding the outer encoded bit stream with convolutional code encoding to generate a convolutional code; and

a puncturing module puncturing at least one bit of the convolutional code to generate the inner encoded bit stream.

7. The MLC memory device of claim 2, wherein the inner encoded bit stream generated by the inner encoder includes a systematic code.

8. The MLC memory device of claim 2, wherein the inner encoded bit stream generated by the inner encoder includes a non-systematic code.

9. The MLC memory device of claim 3, wherein the signal mapping module generates the program pulse according to a Gray coding process.

10. The MLC memory device of claim 2, further comprising:

a signal demapping module generating a demapped bit stream from an output pulse in response to a read signal, the output pulse being output from the MLC memory cell.

11. The MLC memory device of claim 10, wherein the signal demapping module generates the demapped bit stream by performing a hard decision based on the outside pulse.

12. The MLC memory device of claim 10, further comprising:

an inner decoder decoding the demapped bit stream by a first decoding function to generate an inner decoded bit stream, the first decoding function corresponding to the second encoding function.

13. The MLC memory device of claim 12, wherein the signal demapping module generates the demapped bit stream by performing a soft decision based on the output pulse.

14. The MLC memory device of claim 12, wherein the first decoding function includes convolutional code decoding.

15. The MLC memory device of claim 12, wherein the inner decoder includes:

a depuncturing module restoring a punctured bit to the demapped bit stream to generate a depunctured bit stream; and

a mother code decoder decoding the depunctured bit stream with a Viterbi decoding function to generate the inner decoded bit stream.

16. The MLC memory device of claim 12, further comprising:

an outer decoder decoding the inner decoded bit stream by with a second decoding function to generate an outer decoded bit stream, the second decoding function corresponding to the first encoding function.

17. The MLC memory device of claim 1, wherein the MLC memory cell is a memory cell of an MLC flash memory.

18. The MLC memory of claim 1, wherein

the first coding function is a first decoding function and the second coding function is a second decoding function,

the signal module is a signal demapping module generating the demapped bit stream based on data retrieved from the MLC memory cell,

the first coding device is an inner decoder decoding the demapped bit stream based on the second decoding function to generate an inner decoded bit stream, and

the second coding device is an outer decoder decoding the inner decoded bit stream based on the first decoding function to generate an outer decoded bit stream.

19. The MLC memory device of claim 18, wherein the inner decoder is configured to correct an error detected within the demapped bit stream to generate the inner decoded bit stream, and the outer decoder is configured to correct an error detected from the inner decoded bit stream to generate the outer decoded bit stream.

20. The MLC memory device of claim 19, wherein the outer decoder reports an error if an error is detected in the inner decoded bit stream and not corrected.

21. The MLC memory device of claim 18, wherein the signal demapping module generates the demapped bit stream by performing a soft decision based on an output pulse received from the MLC memory cell in order to generate the demapped bit stream.

22. The MLC memory device of claim 18, wherein the MLC memory cell corresponds to an m-bit MLC memory cell with m being a positive integer, and the signal demapping module compares an output pulse received from the MLC memory cell with a threshold voltage of 2^m voltage distributions associated with the MLC memory cell to generate the demapped bit stream corresponding to the output pulse.

23. The MLC memory device of claim 18, wherein the MLC memory cell is a memory cell of an MLC flash memory.

24. A method of performing a data operation with a Multi-Level Cell (MLC) memory device, comprising:

performing a first coding function, the first coding function being one of an encoding function and a decoding function;

performing a second coding function, the second coding function being one of an encoding function and a decoding function; and

performing at least one of instructing a MLC memory cell to store data output as a result of the second coding function if the first and second coding functions are encoding functions, and generating a demapped bit stream based on data retrieved from the MLC memory cell if the first and second coding functions are decoding functions.

25. The method of claim 24, wherein

the first coding function is a first encoding function and the second coding function is a second encoding function.

26. The method of claim 25, further comprising:

encoding data based on the first encoding function to generate an outer encoded bit stream,

encoding the outer encoded bit stream based on the second encoding function to generate an inner encoded bit stream, and

instructing the MLC memory cell to store the inner encoded bit stream as the stored data in the MLC memory cell.

27. The method of claim 24, wherein

the first coding function is a first decoding function and the second coding function is a second decoding function.

28. The method of claim 27, further comprising:

generating the demapped bit stream based on data retrieved from the MLC memory cell;

decoding the demapped bit stream based on the second decoding function to generate an inner decoded bit stream; and

decoding the inner decoded bit stream based on the first decoding function to generate an outer decoded bit stream.