SEMICONDUCTOR MEMORY DEVICE AND METHOD OF ERASING DATA THEREIN

• US 20080137422A1
• Filed: 12/12/2007
• Published: 06/12/2008
• Est. Priority Date: 12/12/2006
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: HOSONO, Koji
• Granted Patent: US 7,733,702 B2
• Time in Patent Office: Days
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells

Abstract

A semiconductor memory device comprises a memory cell array of NAND cell units. The NAND cell unit includes a plurality of electrically erasable programmable nonvolatile memory cells connected serially, and a first and a second selection transistor provided to connect both ends of the memory cells to a bit line and a source line, respectively. The semiconductor memory device also comprises dummy cells inserted in the NAND cell unit adjacent to the first and second selection transistors, respectively. The dummy cells in the NAND cell unit are erased simultaneously with the memory cells under a weaker erase potential condition than that for the memory cells and set in a higher threshold distribution than an erased state of the memory cells.

Claims

1. A semiconductor memory device having a memory cell array configured by arranging a plurality of NAND cell units, said NAND cell unit comprises:

a plurality of electrically erasable programmable nonvolatile memory cells connected serially;

a first and a second selection transistor provided to connect both ends of said memory cells to a bit line and a source line, respectively; and

dummy cells inserted in said NAND cell unit adjacent to said first and second selection transistors, respectively,

wherein said dummy cells in said NAND cell unit are erased simultaneously with said memory cells under a weaker erase potential condition than that for said memory cells and set in a higher threshold distribution than an erased state of said memory cells.

2. The semiconductor memory device according to claim 1, wherein said semiconductor memory device has an erase mode in which an erase voltage is applied to a well region including said memory cell array formed therein, a first voltage of just or near 0 V is applied to control gates of said memory cells in said erase unit, and a second voltage higher than said first voltage is applied to control gates of said dummy cells.

3. The semiconductor memory device according to claim 1, wherein prior to erasing all NAND cell units in said erase unit, preprogramming is executed to selectively elevate the threshold of said dummy cells in said erase unit.

4. The semiconductor memory device according to claim 3, wherein after collectively erasing all NAND cell units in said erase unit, soft-programming is executed for dissolving an over-erased cell in said erase unit.

5. The semiconductor memory device according to claim 1, wherein after erasing all NAND cell units in said erase unit, writing is executed to said dummy cells in said erase unit for setting a higher threshold distribution than said erased state of said memory cells.

6. The semiconductor memory device according to claim 5, wherein after said writing, soft programming is executed for dissolving an over-erased cell in said erase unit.

7. A method of erasing data in a semiconductor memory device, said semiconductor memory device comprising a memory cell array of NAND cell units each including a plurality of electrically erasable programmable nonvolatile memory cells connected serially, and a first and a second selection transistor provided to connect both ends of said memory cells to a bit line and a source line, respectively, and dummy cells inserted in said NAND cell unit adjacent to said first and second selection transistors, respectively, said method comprising:

prior to collectively erasing an erase unit in said memory cell array, executing preprogramming to elevate the threshold of said dummy cells in said erase unit;

collectively erasing all memory cells in said erase unit including said dummy cells under a weaker erase potential condition for said dummy cells than that for said memory cells; and

executing soft-programming for dissolving an over-erased cell in said erase unit.

8. The method according to claim 7, wherein said easier erase voltage condition requires that said voltage applied to control gates of said dummy cells is higher than said voltage applied to control gates of said memory cells.

9. The method according to claim 7, wherein said collective erasing is executed by applying to said control gates of said first and second selection gate transistors a voltage that causes a certain potential difference between said gates and said well region including said memory cell array formed therein.

10. The method according to claim 7, wherein said soft-programming is executed by applying to said gate of said first selection gate transistor a voltage higher than a voltage applied to said gate of said second selection gate transistor, and applying to said control gates of said dummy cells a voltage lower than a voltage applied to said control gates of said memory cells.

11. The method according to claim 7, wherein said soft-programming is executed by applying to gate of said first selection gate transistor a voltage higher than a voltage applied to said gate of said second selection gate transistor, and applying to said control gates of said dummy cells a voltage equal to or higher than the voltage applied to said control gates of said memory cells.

12. A method of erasing data in a semiconductor memory device, said semiconductor memory device comprising a memory cell array of NAND cell units each including a plurality of electrically erasable programmable nonvolatile memory cells connected serially, and a first and a second selection transistor provided to connect both ends of said memory cells to a bit line and a source line, respectively, and dummy cells inserted in said NAND cell unit adjacent to said first and second selection transistors, respectively, said method comprising:

collectively erasing all memory cells in an erase unit in said memory cell array including said dummy cells under a weaker erase potential condition for said dummy cells than that for said memory cells;

executing writing to elevate the threshold of said dummy cells in said erase unit; and

executing soft-programming for dissolving an over-erased cell in said erase unit.

13. The method according to claim 12, wherein said easier erase voltage condition requires that said voltage applied to control gates of said dummy cells is higher than said voltage applied to control gates of said memory cells.

14. The method according to claim 12, wherein said writing is executed by applying to a gate of said first selection gate transistor a first voltage, applying to a gate of said second selection gate transistor a second voltage lower than said first voltage, and applying to control gates of said dummy cells a voltage higher than a voltage applied to control gates of said memory cells.

15. The method according to claim 14, wherein said first voltage is a voltage equal to or lower than a supply voltage, and said second voltage is 0 V.

16. The method according to claim 14, wherein said first voltage is a voltage higher than a supply voltage, and said second voltage is 0 V.

17. A semiconductor memory device having a memory cell array configured by arranging a plurality of NAND cell units, said NAND cell unit comprises:

a plurality of electrically erasable programmable nonvolatile memory cells connected serially;

a first and a second selection transistor provided to connect both ends of said memory cells to a bit line and a source line, respectively; and

a first dummy cell and a second dummy cell inserted in said NAND cell unit adjacent to said first and second selection transistors, respectively,

wherein a first voltage is applied to said first dummy cell prior to apply a second voltage to said second dummy cell in a programming for said memory cell.