SRAM cell with separate read and write ports
First Claim
1. A dual port static random access memory (SRAM) cell comprising:
- at least one inverter coupled between a positive supply voltage (Vcc) and a complementary low supply voltage (Vss) and having an input and output terminals;
at least one PMOS transistor with its gate, source and drain connected to the output terminal, Vcc and input terminal, respectively;
a write port connected to the input terminal and having a write-word-line, a write-enable and a write-bit-line; and
a read port connected to either the input or output terminal and having a read-word-line and a read-bit-line.
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Accused Products
Abstract
This invention discloses a dual port static random access memory (SRAM) cell, which comprises at least one inverter coupled between a positive supply voltage (Vcc) and a complementary low supply voltage (Vss) and having an input and an output terminals, at least one PMOS transistor with its gate, source and drain connected to the output terminal, Vcc and input terminal, respectively, a write port connected to the input terminal and having a write-word-line, a write-enable and a write-bit-line, and a read port connected to either the input or output terminal and having a read-word-line and a read-bit-line.
24 Citations
30 Claims
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1. A dual port static random access memory (SRAM) cell comprising:
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at least one inverter coupled between a positive supply voltage (Vcc) and a complementary low supply voltage (Vss) and having an input and output terminals; at least one PMOS transistor with its gate, source and drain connected to the output terminal, Vcc and input terminal, respectively; a write port connected to the input terminal and having a write-word-line, a write-enable and a write-bit-line; and a read port connected to either the input or output terminal and having a read-word-line and a read-bit-line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A dual port static random access memory (SRAM) cell comprising:
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at least one inverter coupled between Vcc and Vss and having an input and output terminals; at least one PMOS transistor with its gate, source and drain connected to the output terminal, Vcc and input terminal, respectively; a write-word-line, a write-enable and a write-bit-line; a first and a second switching devices connected in series between the input terminal and the write-bit-line, wherein a first control terminal of the first switching device is connected to the write-word-line and a second control terminal of the second switching device is connected to the write-enable; a read-word-line and a read-bit-line; and a third and a fourth switching devices connected in series between a supply voltage and the read-bit-line, wherein a third control terminal of the third switching device is connected to the read-word-line and a fourth control terminal of the fourth switching device is connected to either the input or output terminal. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A dual port static random access memory (SRAM) cell comprising:
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at least one inverter coupled between Vcc and Vss and having an input and output terminals; at least one PMOS transistor with its gate, source and drain connected to the output terminal, Vcc and input terminal, respectively; a word-line, a write-enable, a write-bit-line and a read-bit-line; a first and a second switching devices connected in series between the input terminal and the write-bit-line, wherein a first control terminal of the first switching device is connected to the word-line and a second control terminal of the second switching device is connected to the write-enable; a third and a fourth switching devices connected in series between a supply voltage and the read-bit-line, wherein a third control terminal of the third switching device is connected to the word-line and a fourth control terminal of the fourth switching device is connected to either the input or output terminal. - View Dependent Claims (26, 27, 28, 29, 30)
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Specification