METHOD FOR FABRICATING SOI DEVICE

• US 20080138941A1
• Filed: 02/19/2008
• Published: 06/12/2008
• Est. Priority Date: 05/11/2005
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: PELELLA, Mario M.
• Granted Patent: US 7,741,164 B2
• Time in Patent Office: Days
• US Class Current: 438/154
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/66128 Planar diodes
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes

Abstract

A method is provided for fabricating a semiconductor on insulator (SOI) device. The method includes, in one embodiment, providing a monocrystalline silicon substrate having a monocrystalline silicon layer overlying a monocrystalline silicon substrate and separated therefrom by a dielectric layer. A well region is ion implanted in the monocrystalline silicon substrate. A gate electrode material is deposited overlying the monocrystalline silicon layer. The gate electrode material is photolithographically patterned and etched using a minimum lithography feature size to form a first gate electrode, a second gate electrode and a spacer having the minimum lithography feature size. The gate electrode material is then isotropically etched to reduce the width of the first gate electrode, the second gate electrode and the spacer.

Claims

1. A method for fabricating a semiconductor on insulator (SOI) device having a monocrystalline silicon layer overlying a monocrystalline silicon substrate and separated therefrom by a dielectric layer, the method comprising the steps of:

ion implanting a well region in the monocrystalline silicon substrate;

depositing a gate electrode material overlying the monocrystalline silicon layer;

photolithographically patterning and etching the gate electrode material using a minimum lithography feature size to form a first gate electrode, a second gate electrode and a spacer having the minimum lithography feature size; and

then isotropically etching the gate electrode material to reduce the width of the first gate electrode, the second gate electrode and the spacer.

2. The method of claim 1 further comprising the step of:

ion implanting impurity determining dopant ions into the monocrystalline silicon layer using the gate electrode as an ion implant mask to form spaced apart source and drain regions in the monocrystalline silicon layer;

3. The method of claim 2 further comprising the step of:

ion implanting impurity determining dopant ions into the monocrystalline silicon substrate using the spacer as an ion implant mask to form spaced apart device regions in the monocrystalline substrate.

4. The method of claim 3 further comprising the step of:

electrically contacting the spaced apart device regions.

5. The method of claim 2 wherein the step of ion implanting impurity determining dopant ions into the monocrystalline silicon layer using the gate electrode as an ion implant mask to form spaced apart source and drain regions in the monocrystalline silicon layer comprises the step of:

ion implanting N-type impurity determining dopant ions into the well region of the monocrystalline silicon substrate using the spacer as an ion implant mask to form an N-type device region in the well region of the monocrystalline silicon substrate and into the monocrystalline silicon layer using the first gate electrode as an ion implant mask to form N-channel source and drain regions in the monocrystalline silicon layer.

6. The method of claim 5 wherein the step of ion implanting impurity determining dopant ions into the monocrystalline silicon substrate using the spacer as an ion implant mask to form spaced apart device regions in the monocrystalline substrate comprises the step of:

ion implanting P-type impurity determining dopant ions into the well region of the monocrystalline silicon substrate using the spacer as an ion implant mask to form a P-type device region in the well region of the monocrystalline silicon substrate and into the monocrystalline silicon layer using the second gate electrode as an ion implant mask to form P-channel source and drain regions in the monocrystalline silicon layer.

7. A method for fabricating a semiconductor on insulator (SOI) device having a monocrystalline silicon layer overlying a monocrystalline silicon substrate and separated therefrom by a dielectric layer, the method comprising the steps of:

forming a dielectric isolation region extending through the monocrystalline silicon layer to the dielectric layer;

depositing a layer of gate electrode material overlying the monocrystalline silicon layer and the dielectric isolation region;

patterning the layer of gate electrode material to simultaneously form a gate electrode overlying the monocrystalline silicon layer and a spacer overlying the dielectric isolation region, wherein the gate electrode and the spacer each have a minimum width; and

etching the dielectric isolation region and the dielectric layer using the spacer as an etch mask.

8. The method of claim 7 further comprising the step of:

ion implanting impurity determining dopant ions using the spacer as an ion implantation mask to form spaced apart device regions in the monocrystalline silicon substrate and using the gate electrode as another ion implantation mask to form source and drain regions in the monocrystalline silicon layer proximate the gate electrode.

9. The method of claim 8 wherein the step of ion implanting impurity determining dopant ions to form spaced apart device regions comprises the steps of:

ion implanting a P-type region to form an anode of a substrate diode; and

ion implanting an N-type region to form a cathode of a substrate diode.

10. The method of claim 7 further comprising the step of:

forming a metal silicide layer on the spaced apart device regions.

11. The method of claim 10 further comprising the steps of:

depositing a layer of insulating material overlying the metal silicide layer;

planarizing the layer of insulating material;

etching openings through the layer of insulating material to expose the metal silicide layer; and

forming electrical contacts in the openings to electrically contact the device regions.

12. A method for fabricating a semiconductor on insulator (SOI) device having a monocrystalline silicon layer overlying a monocrystalline silicon substrate and separated therefrom by a dielectric layer, the method comprising the steps of:

forming a dielectric isolation region extending through the monocrystalline silicon layer to the dielectric layer;

ion implanting a well region in the monocrystalline silicon substrate;

depositing a gate electrode layer overlying the monocrystalline silicon layer and the dielectric isolation region;

patterning the gate electrode layer using a photolithographic patterning and etching process to form a P-channel gate electrode and an N-channel gate electrode overlying the monocrystalline silicon layer and a spacer overlying the dielectric isolation region, wherein the P-channel gate electrode, the N-channel gate electrode, and the spacer each have a minimum photolithographic feature size; and

subsequently isotropically etching the spacer to reduce the minimum photolithographic feature size.

13. The method of claim 12 further comprising the step of:

etching through the dielectric isolation region and the dielectric layer using the spacer as an etch mask to expose an anode region and a cathode region spaced apart in the well region of the monocrystalline silicon substrate.

14. The method of claim 13 further comprising the step of:

implanting P-type impurity dopants into the monocrystalline silicon layer to form source and drain regions of a P-channel MOS transistor proximate the P-channel gate electrode and into the anode region in the monocrystalline silicon substrate to form an anode of a substrate diode.

15. The method of claim 14 further comprising the step of:

implanting N-type impurity dopants into the monocrystalline silicon layer to form source and drain regions of an N-channel MOS transistor proximate the N-channel gate electrode and into the cathode region in the monocrystalline silicon substrate to form a cathode of a substrate diode.

16. The method of claim 15 further comprising the step of:

forming a metal silicide in electrical contact with the anode and the cathode.

17. The method of claim 16 further comprising the step of:

depositing an electrically insulating layer overlying the metal silicide;

18. The method of claim 17 further comprising the step of:

etching contact openings extending through the electrically insulating layer to expose a portion of the metal silicide.

19. The method of claim 18 further comprising the step of:

forming electrical contacts contacting the anode and the cathode through the contact openings.

20. The method of claim 19 wherein the step of forming electrical contacts comprises the step of forming conductive plugs filling the contact openings.