MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

• US 20080138971A1
• Filed: 01/07/2008
• Published: 06/12/2008
• Est. Priority Date: 06/14/2004
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamaguchi, Tetsuji, Tokunaga, Hajime
• Granted Patent: US 8,258,030 B2
• Time in Patent Office: Days
• US Class Current: 438/593
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2216/06 Floating gate cells in which the floating gate consists of multiple isolated silicon islands, e.g. nanocrystals
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0104 : Zirconium [Zr]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/07811 : Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

The present invention provides a manufacturing method of a semiconductor device having a semiconductor nonvolatile memory element that is highly reliable and that can increase a variation of a threshold voltage. Further, the present invention provides a method for manufacturing a semiconductor device having a highly reliable semiconductor nonvolatile memory element using a large substrate. According to the present invention, sputtering using, as a target, a solid solution containing silicon that exceeds a solid solubility limit is conducted, so that a conductive film including a conductive layer of a metal element that is a main component of the solid solution and silicon particles is formed, and then, the conductive layer of the metal element is removed to expose silicon particles. Furthermore, a semiconductor device having a semiconductor nonvolatile memory element using the silicon particles as a floating gate electrode is manufactured.

Claims

1. A method for manufacturing a quantum structure, comprising the steps of:

forming a film including a conductive layer and particles formed of silicon over a substrate by sputtering using a target, the conductive layer comprising a metal element; and

removing the conductive layer from the film,

wherein a solid solution containing the metal element and silicon that exceeds a solid solubility limit with respect to the metal element is used as the target.

2. The method for manufacturing a quantum structure according to claim 1, wherein the metal element is one or a plurality of beryllium, aluminum, zinc, gallium, germanium, silver, cadmium, indium, tin, antimony, gold, lead and bismuth.

3. The method for manufacturing a quantum structure according to claim 1, wherein the substrate comprises silicon.

4. The method for manufacturing a quantum structure according to claim 1, wherein the substrate is heated at 300°

C. or less while forming the film.

5. The method for manufacturing a quantum structure according to claim 1, wherein the removing the conductive layer is conducted by wet etching.

6. A method for manufacturing a semiconductor device, comprising the steps of:

forming an insulating film on a semiconductor region over a substrate;

forming a film including a conductive layer and particles formed of silicon on the insulating film by sputtering using a target, the conductive layer comprising a metal element;

removing the conductive layer from the film; and

forming a floating gate electrode by selectively etching the particles formed of silicon,

wherein a solid solution containing the metal element and silicon that exceeds a solid solubility limit with respect to the metal element is used as the target.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the metal element is one or a plurality of beryllium, aluminum, zinc, gallium, germanium, silver, cadmium, indium, tin, antimony, gold, lead and bismuth.

8. The method for manufacturing a semiconductor device according to claim 6, wherein the substrate comprises silicon.

9. The method for manufacturing a semiconductor device according to claim 6, wherein the substrate is heated at 300°

C. or less while forming the film.

10. The method for manufacturing a semiconductor device according to claim 6, wherein the removing the conductive layer is conducted by wet etching.

11. The method for manufacturing a semiconductor device according to claim 6, further comprising steps of:

adding an impurity element to the semiconductor region to form a first impurity region; and

adding an impurity element to the semiconductor region to form a second impurity region,

wherein the concentration of the impurity element of the second impurity region is higher than that of the first impurity region.

12. The method for manufacturing a semiconductor device according to claim 6, further comprising a step of:

forming an impurity region comprising a silicide in the semiconductor region.

13. A method for manufacturing a semiconductor device, comprising the steps of:

forming an insulating film on a semiconductor region over a substrate;

forming a film including a conductive layer and particles formed of silicon on the first insulating film by sputtering using a target, the conductive layer comprising a metal element;

oxidizing the conductive layer to form a metal oxide film; and

forming a floating gate electrode by selectively etching the metal oxide film and the particles formed of the silicon,

wherein a solid solution containing the metal element and silicon that exceeds a solid solubility limit with respect to the metal element is used as the target.

14. The method for manufacturing a semiconductor device according to claim 13, wherein the metal element is one or a plurality of beryllium, aluminum, zinc, gallium, germanium, silver, cadmium, indium, tin, antimony, gold, lead and bismuth.

15. The method for manufacturing a semiconductor device according to claim 13, wherein the substrate comprises silicon.

16. The method for manufacturing a semiconductor device according to claim 13, wherein the substrate is heated at 300°

C. or less while forming the film.

17. The method for manufacturing a semiconductor device according to claim 13, wherein the oxidizing the conductive layer is conducted by GRTA method.

18. The method for manufacturing a semiconductor device according to claim 13, wherein the oxidizing the conductive layer is conducted by LRTA method.

19. The method for manufacturing a semiconductor device according to claim 13, further comprising steps of:

adding an impurity element to the semiconductor region to form a first impurity region; and

adding an impurity element to the semiconductor region to form a second impurity region,

wherein the concentration of the impurity element of the second impurity region is higher than that of the first impurity region.

20. The method for manufacturing a semiconductor device according to claim 13, further comprising a step of:

forming an impurity region comprising a silicide in the semiconductor region.